Could anyone gimme code for SR flip flop? i.e., its a combinational circuit. How do i write a structural architecture for an SR flip flop which is composed of 2 NOR gates. My major problem in writing code for this is, the state transition table. i.e., when the present state and the inputs are "00", the output is "11", then with "11 as the present state and "00" as input, the output changes to "00", so the output keeps oscillating between "00" and "11".
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structural arch. for combinational ckt. - help pls.
- Thread starter xyz987
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First - I am brand new one in this place
I do hope my message will reach the target and will not bother anyone
))
Now
You are trying to construct the VHDL code for the combinatorial circuit with the feedback.
You can write the VHDL code - just connect the gates ... and it will be the proper structural description. OK.
But the reasonable simulation results are not guaranteed. The simulator does the iterative analysis of the logical network with the current stimuli conditions until it gets the stable state of all the nodes. For combinatorial circuits (i.e no Flip-flops) with feedback this stable state may just never be found.
Eventually it may happen that the simulator gets into the neverending loop of the analysis.
In the real world the combinatorial circuits with the feedback are either the devices with memory (registers)
or some incredible generators which shall be analysed as analogue circuits ...
For the first case we use the typical behavioural but synthesizable description of the regs (process etc). The second case is the reason why we never do it))
The question arises - why are you doing that ?
Is it a kind of study or a homework?
(Did some teacher mean it a kind of stimuli to consider the issues I have written above? Did I spoil his job then?)
regards
anyway
I do hope my message will reach the target and will not bother anyone
))Now
You are trying to construct the VHDL code for the combinatorial circuit with the feedback.
You can write the VHDL code - just connect the gates ... and it will be the proper structural description. OK.
But the reasonable simulation results are not guaranteed. The simulator does the iterative analysis of the logical network with the current stimuli conditions until it gets the stable state of all the nodes. For combinatorial circuits (i.e no Flip-flops) with feedback this stable state may just never be found.
Eventually it may happen that the simulator gets into the neverending loop of the analysis.
In the real world the combinatorial circuits with the feedback are either the devices with memory (registers)
or some incredible generators which shall be analysed as analogue circuits ...
For the first case we use the typical behavioural but synthesizable description of the regs (process etc). The second case is the reason why we never do it
))The question arises - why are you doing that ?
Is it a kind of study or a homework?
(Did some teacher mean it a kind of stimuli to consider the issues I have written above? Did I spoil his job then?)
regards
anyway
Im not quite sure on your definition of present state and output here. I am assuming that present state is the output before the SR inputs change, and output is the output after the change.
I also assume that your two outputs are Q and not Q.
Which brings me to the question. How did your Q and not Q get to the same value? (you state that present state and inputs are both "00".
The answer to that question would seem to be that at some point in time you violated the "never set both set and reset together" rule.
In your example your imputs seem to be "00" which is okay (unless you have inverted inputs like you would have with a NAND implementation), but I suspect that some time previous to this you had inputs of "11". That is bad.
A quick example of the logic (for an unclocked SR flop) would be
SRFLOP : process (R, S, notQ, Q)
begin
Q <= R nor notQ;
notQ <= S nor Q;
end process SRFLOP;
Note that this is not using "structural" code which I assume means creating your own NOR entity and instantiating it twice with the appropriate wires hooked up.
I also assume that your two outputs are Q and not Q.
Which brings me to the question. How did your Q and not Q get to the same value? (you state that present state and inputs are both "00"
.The answer to that question would seem to be that at some point in time you violated the "never set both set and reset together" rule.
In your example your imputs seem to be "00" which is okay (unless you have inverted inputs like you would have with a NAND implementation), but I suspect that some time previous to this you had inputs of "11". That is bad.
A quick example of the logic (for an unclocked SR flop) would be
SRFLOP : process (R, S, notQ, Q)
begin
Q <= R nor notQ;
notQ <= S nor Q;
end process SRFLOP;
Note that this is not using "structural" code which I assume means creating your own NOR entity and instantiating it twice with the appropriate wires hooked up.
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