String comparison within an if statement

[ROOZ123]

Hi everyone,
I am new here and i am going to start my first thread by a very simple question. I would like to know how i could compare an string within an if statement.

entity
memory_model :in string;
..
end ..;

architecture ...of .. is
process(..)
begin
if( memory_model="dual_port") then
............
endif
end ...;
right now i get an error that memory_model is not a signal
could someone please help me with this?

 

[jeandelfrigo]

ROOZ123,

I haven't uses strings like that before, because I usually write RTL code that synthesizes.

Your code extract is also limmited so I do not know what you want to do.

Whate I'm thinking of is that you need generics.

Lets say you're writting a memory element that can work in dual or single port mode.
Than you can use a generic that defines the mode and you can use the if generic = "ccccccccc" generate statement.

This basically means that you describe both configurations in the VHDL code and that the generic value will determine the mode that gets implemented at compile time.

I suggest you google for generics and VHDL and Generate and VHDL for more info.

If you want to have both modes available during run time you need to create two separate instances, that will use their own logic and add selection logic between both.

In some cases you could use dynamic mode selection, but keep in mind that these things get rather complex really easy and so the best way is most of the time to foresee both instances.

regards

jeandelfrigo