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std_uloigc_vectors?
- Thread starter xyz987
- Start date
I have never tried it with unresolved types, but you could probably typecast it to unsigned. (you will need a library declaration with unsigned type).
abc <= std_ulogic_vector(unsigned(def) + unsigned(ghi));
but tell me. Why are you using unresolved types?
As opposed to std_logic and std_logic_vector.
I ask this question because I don't really know unresolved types, when they should be used and for what reasons.
--
abc <= std_ulogic_vector(unsigned(def) + unsigned(ghi));
but tell me. Why are you using unresolved types?
As opposed to std_logic and std_logic_vector.
I ask this question because I don't really know unresolved types, when they should be used and for what reasons.
--
aaah to answer my own question:
The std_ulogic data type is an unresolved type, meaning that it is illegal for two values (such as '0' and '1', or '1' and 'Z') to be simultaneously driven onto a signal of type std_ulogic. If you are not describing a circuit that will be driving different values onto a wire (as you might in the case of a bus interface), then you might want to use the std_ulogic data type to help catch errors (such as incorrectly specified, overlapping combinational logic) in your design description. If you are describing a circuit that involves multiple values being driven onto a wire, then you will need to use the type std_logic. Std_logic is a resolved type based on std_ulogic.
taken from:
--
The std_ulogic data type is an unresolved type, meaning that it is illegal for two values (such as '0' and '1', or '1' and 'Z') to be simultaneously driven onto a signal of type std_ulogic. If you are not describing a circuit that will be driving different values onto a wire (as you might in the case of a bus interface), then you might want to use the std_ulogic data type to help catch errors (such as incorrectly specified, overlapping combinational logic) in your design description. If you are describing a circuit that involves multiple values being driven onto a wire, then you will need to use the type std_logic. Std_logic is a resolved type based on std_ulogic.
taken from:
--
(Very good explanation VHDLguy 
))
Please let me add something more ... some explanation first
Generally for both the std_logic_vector and std_ulogic_vector you cannot make any arithmetical operations because these types represent just a fistful of bits. As long as they're not organised - i.e we do not precise which bit is the MSB, which is LSB and especially whether is it "always positive" or 2'complement none arithmetic operatiomn would make any sense.
(This is the basic thing to remember.)
NEVERTHELESS for std_logic_vector there are two packages
available - namely
ieee.std_logic_unsigned and ieee.std_logic_signed
which provide arithmetic operations + - * under conditions taht you decide whether you go for "always positive" or 2'complement interpretation of the vectors given. You must decide and you must select only one of them - signed/unsigned
And this is the common practice - keeping close to the hardware, using this instead of e.g. integer.
Unfortunately - according to my best knowledge - nothing like that is available for std_ULOGIC_vector directly.
(BUT YOU CAN TRY TO FIND !!!)
(probably because std_ULOGIC_vector is commonly perceived as something strange whilst the std_LOGIC_vector is the industrial standard indeed, so the folks from IEEE simply fook that ?)
Thus the most natural way would be either to move for std_LOGIC or just locally change the type of your signals.
("VHDL is type oriented" they say smoooothly). Because the changing of a type in this case is something natural and simple you can "just do it".
Sorry for this extra-long lecture.
See a short study code below. See all the libraries and packages needed. And that I have, for the moment, decided for "always positive" interpretation of the fistful of bits. See the differences for both types on the left and on the right. Please play more with it .... and have fun.
It works. It is synthesizable. Hope it explains definitely.
---------------------------------------------
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity aa is
port(
a : in std_ulogic_vector(7 downto 0);
b : in std_ulogic_vector(7 downto 0);
z : out std_ulogic_vector(7 downto 0));
end aa;
architecture aa_a of aa is
signal c : std_logic_vector(7 downto 0);
begin
c <= std_logic_vector(a) + "00010001";
z <= std_ulogic_vector(c + std_logic_vector(b));
end aa_a;
))Please let me add something more ... some explanation first
Generally for both the std_logic_vector and std_ulogic_vector you cannot make any arithmetical operations because these types represent just a fistful of bits. As long as they're not organised - i.e we do not precise which bit is the MSB, which is LSB and especially whether is it "always positive" or 2'complement none arithmetic operatiomn would make any sense.
(This is the basic thing to remember.)
NEVERTHELESS for std_logic_vector there are two packages
available - namely
ieee.std_logic_unsigned and ieee.std_logic_signed
which provide arithmetic operations + - * under conditions taht you decide whether you go for "always positive" or 2'complement interpretation of the vectors given. You must decide and you must select only one of them - signed/unsigned
And this is the common practice - keeping close to the hardware, using this instead of e.g. integer.
Unfortunately - according to my best knowledge - nothing like that is available for std_ULOGIC_vector directly.
(BUT YOU CAN TRY TO FIND !!!)
(probably because std_ULOGIC_vector is commonly perceived as something strange whilst the std_LOGIC_vector is the industrial standard indeed, so the folks from IEEE simply fook that ?)
Thus the most natural way would be either to move for std_LOGIC or just locally change the type of your signals.
("VHDL is type oriented" they say smoooothly). Because the changing of a type in this case is something natural and simple you can "just do it".
Sorry for this extra-long lecture.
See a short study code below. See all the libraries and packages needed. And that I have, for the moment, decided for "always positive" interpretation of the fistful of bits. See the differences for both types on the left and on the right. Please play more with it .... and have fun.
It works. It is synthesizable. Hope it explains definitely.
---------------------------------------------
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity aa is
port(
a : in std_ulogic_vector(7 downto 0);
b : in std_ulogic_vector(7 downto 0);
z : out std_ulogic_vector(7 downto 0));
end aa;
architecture aa_a of aa is
signal c : std_logic_vector(7 downto 0);
begin
c <= std_logic_vector(a) + "00010001";
z <= std_ulogic_vector(c + std_logic_vector(b));
end aa_a;
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