std_logic_vector vs integer

[GrimSleepers]

I am fairly new to VHDL and have reviewed numerous codes and have tried to learn various programs [Xilinx, Altera, etc.,] What I have found in many examples is the use of 'std_logic_vector' used as counters versus using 'integers'. Is there an advantage or reason for this type of use? For example, in a telemetry system, a frame sync is timed to go to a '1' at count "0000000100101010" [298] and then '0' at count "0011111111111111" [16383] of a 5MHz clock and resets and counts up again.

 

[RVSachin]

Std_logic_vector is same as integer. Whatever integer value is specified, it is implemented as bus of appropriate size subsequently.

So, declaring a bus for instance,
temp: std_logic_vector(3 downto 0)
is same as
temp: integer range 0 to 15
because both require 4-bit wide bus.

However, note that, if required range is not specified for the integer type, then it will occupy 32-bit bus, by default.