Starter question about teh rotary example

[zsotya]

Hello!

I am new in the VHD, it is hard but i like learn. I found some code wat i realy can't understand alone.
The example program come from the Xilinks webpage:

http://www.xilinx.com/products/boards/s3estarter/files/s3esk_rotary_encoder_interface.zip

What i dont understand can found in the DIRECTION process.

direction: process(clk)
begin
if clk'event and clk='1' then

delay_rotary_q1 <= rotary_q1;
if rotary_q1='1' and delay_rotary_q1='0' then
rotary_event <= '1';
rotary_left <= rotary_q2;
else
rotary_event <= '0';
rotary_left <= rotary_left;
end if;

end if;
end process direction;


I dont understand these two lines:
delay_rotary_q1 <= rotary_q1;
if rotary_q1='1' and delay_rotary_q1='0' then

In this case lookslike otary_q1 and delay_rotary_q1 every time contain same value and the if statement newer will be true. But i think it is just lookslike... But why? How does it work? Why need this?

Thanks for the help and sorry for the poor english!

Zsolt

 

[jeandelfrigo]

Zsolt,

This is a one of many ways to do edge detection.

direction: process(clk)
begin
if clk'event and clk='1' then

delay_rotary_q1 <= rotary_q1;
if rotary_q1='1' and delay_rotary_q1='0' then
rotary_event <= '1';
rotary_left <= rotary_q2;
else
rotary_event <= '0';
rotary_left <= rotary_left;
end if;

end if;
end process direction;

They use a clocked process, this means very (rising) clock edge the rotary_Q1 signal is sampled in delay_rotary_Q1. The also every clock edge they look at the values of the signal and the delayed value. if the signal becomes one and the 1 clock delayed value is still zero then there is a rising edge of the signal.

Now if you're used to software this is confusing, but this is VHDL and thus hardware. Altough this is written in one process (I agree it might be confusing for people new to VHDL) rotary_Q1 and delay_rotary_Q1 do not allways have the same value. In fact the differ one clock period on rising and falling edges. This is because delay_rotary_Q1 is only asigned the value of rotary Q1 at the end of the process, so after the evaluation at that same clock edge.

So you have the following:

1) rotary_Q1 becomes '1'
2) a positive clock edge occurs (clk'event and clk = '1')
2.1) the delayed signal will get the value of rotary_Q1 but after the clock edge (end of process) this is called clock to output delay of a flipflop or register.
2.2) at the same time (rising clock edge the evaluation is made and is true rotary is '1' but the delayed version of rotary still is '0', so the code in the if is performed.
3) the following rising clock edge rotary is still '1' but now so is the delayed version so the condition is no longer true and the else is performed.

Again I know this is difficult at first, especially when your used to C for example.
The thing is that it sometimes helps to synthesize a process "by hand", then you will see that although it is written in one process it ends up in different registers. Of course when you're new at VHDL this is equally difficult or even more difficult to do.

Anyhow good luck and I hope my explanation was somewhat useful.

regards

jeandelfrigo