Simple Problem: i/o declaration error

[JayHandle]

Hello,

I'm just learning about VHDL components and I'm having a problem with the i/o ports being undeclared in the top level of the hierarchy. Synopsis vhdlan compiles the program perfectly, but vhdldbx (the debugger/simulator) will state that the port names are undeclared the second time I try to apply the stimulus to port name InDB.

The code is simple, two inverters are connected, one after the other. I'm trying to apply a stimulus to InDB (more than once!) without the error that InDB is undeclared - which you only get the second time (or later) that you try to apply a stimulus in the debugger. Quite frustrating for a beginner!

-JayHandle
The code is given below:-



--first inverter
library ieee;
use ieee.std_logic_1164.all;

entity jNOT1 is
port (
In1 : in std_logic;
Out1 : buffer std_logic
);
end jNOT1;
architecture dataflow_jNOT1 of jNOT1 is
begin
process_jNOT1 : process(In1)
begin
Out1 <= not(In1);
end process process_jNOT1;
end dataflow_jNOT1;


library ieee;
use ieee.std_logic_1164.all;


--second inverter
entity jNOT2 is
port (
In2 : in std_logic;
Out2 : buffer std_logic
);
end jNOT2;
architecture dataflow_jNOT2 of jNOT2 is
begin
process_jNOT2 : process(In2)
begin
Out2 <= not(In2);
end process process_jNOT2;
end dataflow_jNOT2;


library ieee;
use ieee.std_logic_1164.all;
use work.all;

--current problem, InDB is considered undeclared by simulator...
--two inverters together
entity DoubleBuf is
port(InDB : in std_logic; OutDB : buffer std_logic);
end DoubleBuf;

architecture STRUCTURAL_DoubleBuf of DoubleBuf is
signal S1: std_logic; --internal interconnection signal declared

component jNOT1 --component declared
port(In1: in std_logic; Out1: buffer std_logic); -- port names must match original entity above
end component;

component jNOT2 --component declared
port(In2: in std_logic; Out2: buffer std_logic); -- port names must match original entity above
end component;

begin

A1: jNOT1 port map(InDB,S1); --instantiation of component
B1: jNOT2 port map(S1,OutDB); --instantiation of component

process_DoubleBuf : process(InDB) -- process comes after component declaration and instantiation
begin
end process process_DoubleBuf;

end STRUCTURAL_DoubleBuf;


-- configuration statement required to define top of hierarchy prior to simulation
-- otherwise an error will result

configuration ConfigDoubleBuf of DoubleBuf is
for STRUCTURAL_DoubleBuf
end for;
end ConfigDoubleBuf;

 

[JayHandle]

I've solved my own problem...

The problem was that as the Synopsys simulator traverses the hierarchy, it goes through different entities, and changes its current view of the port names/variables/signals. Therefore, when assigning values, always use the full path name to avoid the &quot;undeclared variable&quot; error.

general example:
assign '1' /topHierarchy/portName