Signed numbers: Adding 2 negative numbers

[clarksa]

I'm trying to port the following C code to VHDL using 1164 and numeric_std:

int L = minR*8 - 128;

int R = minL*8 - 128;

newspeed = R + L;

newturnrate = R - L;

I can do the multiplications and subtractions. I run into problems when L and R are both negative numbers and I try to add them:

C: newspeed = r+l

VHDL : mvspd_DI <= std_logic_vector(signed(L_R4) + signed(R_R5));

I can see that the bitfields are simply being added, for example:

x"FFF8" is supposed to represent -8 with sign extension
x"FF80" is supposed to represent -128 with sign extension

But when I add the 2 numbers using the above VHDL line the result is a plain old bitfield add. Result x"FF78".

Do I have to write my own hardware that does 2's complement arithmetic?

In short:

How do I treat std_logic_vectors like signed integers to do signed adding and subtracting?