signal problem

[fayevalentine]

Hello all,

I have a little problem I hope someone of you can help me.

I have two entities e1 and e2, and e2 needs a signal s1 from e1,

when I make instances of e1 and e2 in a third module e3
the three entities follow a clk_main, then when a simulate e3 the signal takes 2 cycles to came from e1 to e2, I know that this is because the signal s1 takes the value I need in the next cycle because of its driver but I need that value immediately, I can not use a variable because I work inside a process.


how can I obtain the value in one cycle?
is this possible?

Thanks in advance.

 

[BertVhdl]

Hi,

First of all: Why is it necessary that you obtain the signal immediately?

And second: If you want to do it without delay, you need to remove all register in that signal, but be very carefull with this because of timing issues!!!