signal generator

[UlfKenneth]

How do I make a signal generator with VHDL?
It should look someting like this.

HI: a number of clockpulses
LOW: another number of clockpulses

 

[RVSachin]

HERE is the CODE for your requirement:

--_________________________________________
architecture rtl of cnt is

signal cnt: integer range 0 to 2;

begin

Process(clk)
begin
if rising_edge(clk) then
if cnt = 2 then
cnt <= 0;
clk2 <= '1';
else
cnt <= cnt + 1;
clk2 <= '0';
end if;
end if;
end process;
end rtl;

 

[UlfKenneth]

thanks a lot.. it works great..