signal does not hold its value outside clock edge

[al1715]

Hi
I have problem with my code, need some help please.

If I erase the comment-dashes so I get State A3 from A2 when
C_In go from 0 to 1, then I get the error message :

VHDL error : can't infer register for signal State.a3 because signal does not
hold its value outside clock edge

Why does it work from State A1 to A2 but not for A2 to A3 ?

Thanks in advance

--------------------------------------------------------------
Entity Driver Is
port
(
A_In, C_In ,reset: In Std_Logic;
Data_Out : Out Std_Logic
);
End Entity;

architecture structure of Driver is

type State_type is (START,A1,A2);
--type State_type is (START,A1,A2,A3);

signal State : State_type;

begin

process(reset,C_In,A_In,State)
begin
if reset = '1' then
State <= START;
elsif (A_In='0' AND State = START) then
State <= A1;
elsif (rising_edge(C_In) AND State = A1) then
State <= A2;
-- elsif (rising_edge(C_In) AND State = A2) then
-- State <= A3;
end if;

end process;

process(State)
begin
case State is
When START =>
Data_Out <='Z';
when A1 =>
Data_Out <='0';
when A2 =>
Data_Out <='Z';
-- when A3 =>
-- Data_Out <= '1';
end case;
end process;

end structure;

 

[jeandelfrigo]

Al1715,

I don't really understand what your trying to do here.
You have a state machine but the state signal is either clocked and not clocked.

Normally state machines are allways synchronous :

A first way of describing a FSM is single process, this means you write your FSM (register and next state logic) and output logic in a single process.

For example :

FSM1 : process(Rst,Clk)
begin
if (rst = '1')then
FSM1_state <= START;
FSM1_OUT <= "001";
elsif(clk'event and clk = '1')then
if(inputA = '1' and FSM1_state = START)then
FSM1_state <= ONE;
output <= "110";
end if;
if(inputB = inputC and FSM1_state = ONE)then
FSM1_state <= TWO;
output <= "000";
end if;
if(FSM1_state = TWO)then
output <= output + 1;
if (inputA = '0')then
FSM1_state <= START;
end if;
end if;
end if;
end process FSM1;

This is just a FSM I made up, it has no other purpose than syntax demonstration.

A second method is the two process method :

you have a sequential process and then a combinatorical one for the next state logic. I'll explain describing a counter with some status flags.

count_sync : process(rst,clk)
begin
if(rst = '1')then
counter <= (others => '0');
elsif(clk'event and clk = '1')then
counter = next_counter;
end if;
end process count_sync;

count_comb : process(counter,upnotdown)
begin
counterMaxVal <= '0';
counterMinVal <= '0';
case counter is
when "00" => if(upnotdown = '1')then
next_counter <= counter + 1;
else
next_counter <= counter;
end if;
counterMinVal = '1';
when "01" => if(upnotdown = '1')then
next_counter <= counter + 1;
else
next_counter <= counter - 1;
end if;
when "10" => if(upnotdown = '1')then
next_counter <= counter + 1;
else
next_counter <= counter - 1;
end if;
when "11" => if(upnotdown = '1')then
next_counter <= counter;
else
next_counter <= counter - 1;
end if;
counterMaxVal <= '1';
when others => next_counter <= "00";
end case;
end process count_comb;

You can also choose to do the output assignments in a third seperate process that can be clocked or not, this is up to you and the application of course.

But most important is that the state of a FSM is always registered.
You might want to try asynchronous state machines if you want to, but i do not advise it. But making a half synchronous and half asynchronous state machine makes no sense.

Best regards

Jeandelfrigo