signal assignment inside a for loop

[krkrkr]

Hello all,
I'm new to VHDL and having a problem.

I know that signal assignment does not take effect until the end of the process unlike the variable assignment.
ie cnt <= cnt +1;
out <= cnt;
If cnt is a signal then out will have the value of cnt before adding 1.

My problem is I want to have same kind of signal assignment inside a for loop
ie for i 0 to 2 loop
cnt <= cnt +1;
end loop;

cnt is a signal, how can i do that and have the right cnt value?

Thanks.

 

[Robbe147]

Try this:

process
variable cntvar: natural;
begin
cntvar := cnt;
for i 0 to 2 loop
cntvar := cntvar + 1;
end loop;
cnt <= cntvar;
end process;