Sequential mapping Error

[jvet4]

I have the following code that I am trying to synthesize using FPGA Express VHDL. I am getting the error &quot;Sequential mapping has detected that the cell '/counter-optimized/current_count_reg<0>' uses both the asynchronous 'set' and 'clear' pins.&quot; for all 32 bits in the current count register. I know the problem is being caused by the last two lines in which the 32 bit vector is being bit sliced into 2-16 bit vectors (this was tested by commenting out those lines)

My question is two fold: 1. How can I prevent this error and still be able to output the two bit slices, and 2. how can I output the two bit slices using an if statement (i.e. if run = '1' then <output the bit slices> else <bit slices <= '0'>.

Thank You
------------------------------------------------------------

entity counter is
Port (
run: in STD_LOGIC; --start @ 0 to put preset hi and low into current_count
reset: in STD_LOGIC;
clk1k : in STD_LOGIC; --1kHZ clock
preset_low: in STD_LOGIC_VECTOR(15 downto 0);
preset_hi: in STD_LOGIC_VECTOR(15 downto 0);
count_low: out STD_LOGIC_VECTOR(15 downto 0);
count_hi: out STD_LOGIC_VECTOR(15 downto 0)
);
end counter;

--------------------------------------------------------------------------------------------
architecture counter of counter is

signal current_count: STD_LOGIC_VECTOR(31 downto 0); --value of current count
signal max_count: STD_LOGIC_VECTOR(31 downto 0); --max count value

begin
max_count <= &quot;11111111111111111111111111111111&quot;;

reg_count:
process(reset, clk1k)
begin
if reset = '1' then
current_count <= preset_hi & preset_low;
elsif (clk1k'event and clk1k = '1') then
if current_count < max_count then
current_count <= current_count + &quot;1&quot;;
elsif current_count = max_count then
current_count <= (others => '0');
end if;
end if;
end process;

count_hi(15 downto 0) <= current_count(31 downto 16);
count_low(15 downto 0) <= current_count(15 downto 0);




end counter;

 

[RVSachin]

Hi,
I am not sure why you would use some logic at the reset condition and assign it to the output. The logic AND at reset is resulting in the FF with both S-R.

Secondly, the counter you intend to write looks like a simple up-counter where you want the counter to start all over again from the scratch once it reaches the maximum count value possible. If this is the case, then you need not write the following lines:

if current_count < max_count then
current_count <= current_count + &quot;1&quot;;
elsif current_count = max_count then
current_count <= (others => '0');

Instead, you can just have the counter assignment only, as the counter will automaically reset once it reaches a all '1's value.

And for the second question you have put, just see the last two assignments I have made in the modified code I have included here.

Hopefully, this should solve your problem.

- RV





--------------------------------------
process(reset, clk1k, preset_hi , preset_low)
begin
if reset = '1' then
current_count <= preset_hi & preset_low;
elsif (clk1k'event and clk1k = '1') then
current_count <= current_count + &quot;1&quot;;
end if;
end process;

count_hi(3 downto 0) <= current_count(7 downto 4) when run = '1' else (others => '0');
count_low(3 downto 0) <= current_count(3 downto 0) when run = '1' else (others => '0');

end counter;

 

[jvet4]

Thanks for the response. I thought about the counter resetting after I sent the original question, the code that i have been using actually is similiar to the one provided. However, using the declaration:

count_hi(3 downto 0) <= current_count(7 downto 4) when run = '1' else (others => '0');
count_low(3 downto 0) <= current_count(3 downto 0) when run = '1' else (others => '0');

still gives me the same &quot;asynchronous 'set' and 'clear' pins&quot; error during synthesis. Is there a different work around? I know that this statement works in VHDL 93, but it seems to hang up in 87