selective assignment using if/else without process

[hemang]

Hi,
I want to know if there is any way in VHDL to select signal assignment using if/else statements without using it in process.
e.g. I have following code :
sigA((12 - width) downto 0) <= sig_GND;

Now, this statement is true only when width = 12 or less. For other values of width, it will fail , hence I need to write some thing like, when width >= 12, don't use this signal assignment.
How do I do that in VHDL? If I use &quot;when&quot; statement, then also how do I state that don't use this signal ?
your help is appreciated.

 

[SMundschau]

Since width appears to be a generic in your design, you should be able to use a GENERATE statement:

assignment : if width <= 12 generate
sigA((12-width) downto 0) <= sig_GND;
end generate assignment;