RLS 4.5 Clocks on 2616.s

[harris215]

The clock display on 2616 is about 3 hours ahead of actual time. I did a search and found were patch
MPLR17694 needs to installed and in LD77 DLMP 0/1 needs to be set to 0 is this still correct.

 

[Firebird Scrambler]

I've found these details below

Brief Detail....Since upg to 4.5 and CPP4 Time Drift
Condition..CS1000M 3621 CP4 Rls 4.50W
Action....None Specific
Expected Response....Norm Clock
Actual Response....Clock runs slow/fast
Add Info...
We have seen clock drift slow since we have had
4.5 cpp4 can be 2-4 minutes per week.
Only seen since CTI group complained because of symposium..
We have now received from all 4.50 pentium processor sites same complaint.


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The digital sets take their time from the Cpu via the controller to the phone.
Once the time has been downloaded the clock is controlled from the phone.
The running of lamp audits (Ovl 77) down loads the time from the Cpu to the controller to the phone 2 hours before the midnight routines.
If the Lamp Audits are turned off the time on the digital sets may drift.


Firebird Scrambler
Nortel Meridian 1 / Succession and BCM / Norstar Programmer in the UK
Advance knowledge on BCM support

http://www.linkedin.com/in/davidbromley