rising and falling edge trigger

[agunos]

Is it possible to trigger off both the rising and falling edge of the clock? I try doing this a nubmer of ways and when I go to synthesize, I get errors. All the examples I have seen only incorporate rising edge clock triggers. Thanks for any help. Hopefully I have given enough information.

 

[RVSachin]

No, you cannot trigger a design with both rising_edge and falling edge of the clock. This is invalid.

 

[Srika]

Of course u can do it

Clk'event and (clk='1' or clk='0')

This probably shouldn't have any problem.Any way I don't get the purpose of u trying this.If u could tell me the exact context I'd appreciate it.

srikanth

 

[Srika]

No the code is not synthesisable.But
in a simulation point of view,This is correct

 

[RVSachin]

Hi Srika,

I would like to clarify that when I said triggering something on both edges of CLK is invalid, I definetely meant in persepective of SYNTHESIS only.

After all, what is the issue if something can be simulated, but cannot put into a chip?

RAVI.

 

[avib]

Hi,
I think that it depends on the target device if it support both rising or falling edge
Avi