Report at Exit

[xyz987]

How do i give a report statement which should be printed only at the exit. i.e., I want to give a report statement in a testbench to indicate finally that the whole test was succesful.

 

[VHDLguy]

Well there are probably thousands of ways and it would really depend on the structure of your test.

For example the following thread:
thread284-675421 a file IO operation that seems to be part of a testbench, and it seems that the end of the file marks the end of the test so he has a loop to read the file and when he is done an assert statement with severity failure.

Thats one possible way that is commonly used.

Any more specifics?

 

[xyz987]

but what if i have the whole process repeating itself for as long as u run it. For example, when i am simulating a 3 bit decoder, for as long as I run the testbench, it keeps giving inputs and checking the outputs, repeating the cycle. Then how do I do it?

 

[VHDLguy]

You are going to need some way to define the end of a test.

Examples are:
specific time
end of file
some error
some event being successful x number of times.

Then use an assert statement to break. (note that different simulators break on different assertion levels. usually you can change the break level.)

I don't think there would be any way to simply detect when the simulator is no longer running. (ie say you say run 200 us).

I guess if you were to run a batch command in a simulator you could use something like force. Have an End of Test signal and use your simulator to force that signal to a different value, then run the test a little longer until that signal generates an assert with the information you need.

What defines the end of a test in your case? How are you running the test (ie would a batch solution be ok?)