Tek-Tips is the largest IT community on the Internet today!

Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!

Register Log in
  • Congratulations Mike Lewis on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!

Reed Solomon 255, 223 VHDL implementation

Status
Not open for further replies.
yongsong

yongsong

Programmer
Mar 12, 2003
2
0
0
SG
Hi,
I'm implementing Reed Solomon (255,223) on FPGA using VHDL. Before hand, I've implemented a RS(15,11) as a prototype and it works fine. However, i faced trouble when i try upscale it to (255,223) which used up a huge number of gates and slices. I believe this is mainly due to the finite field conversion(exponential to binary) table implemented in the code.

Is there any way shorter/more effective way of implementating the finite field conversion?
any other ideas on the code are welcomed!!! Please help!! Thanks in advance!!
 
Status
Not open for further replies.

Similar threads

AAJR72
  • Locked
  • Question
VHDL testbench
Replies
0
Views
57
AAJR72
AAJR72
Konstantinosdms
  • Locked
  • Question
Question about MIPS on vhdl
Replies
0
Views
55
Konstantinosdms
Konstantinosdms
confabio
  • Locked
  • Question
VHDL state machine
Replies
0
Views
56
confabio
confabio
ClyntonBR
  • Locked
  • Question
VHDL for simulation in ModelSim or Quartus II.
Replies
0
Views
54
ClyntonBR
ClyntonBR
indoubt
  • Locked
  • Question
VHDL erro: "NUMERIC_STD.">": metavalue detected, returning FALSE"
Replies
0
Views
67
indoubt
indoubt

Part and Inventory Search

Sponsor

Back
Top