Tek-Tips is the largest IT community on the Internet today!

Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!

  • Congratulations IamaSherpa on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!

Questions on Syntac

Status
Not open for further replies.

marina23

Programmer
Dec 7, 2005
1
GB
Hello!

Can we have concurrent statements such as port mapping inside if statements?

IS there a do-while command in VHDL?

Thanks
Marina
 
port mapping or such is not possible in if statement, but you could generate a control signal in a process, and use it to select the mapped signals (by "... when ..." or "with ... select") .( I hope this is what you're looking for.
about the do-while, yes there is. it's this way:
[label : ] while condition loop
{ sequential_statement }
end loop [label];
FPGA express manual advises a wait statement in the loop if the condition is incomputable, that is the synthesizer can't determine hen it becomes true, and it's dependent on some signals.
 
Status
Not open for further replies.

Part and Inventory Search

Sponsor

Back
Top