port mapping or such is not possible in if statement, but you could generate a control signal in a process, and use it to select the mapped signals (by "... when ..." or "with ... select" .( I hope this is what you're looking for.
about the do-while, yes there is. it's this way:
[label : ] while condition loop
{ sequential_statement }
end loop [label];
FPGA express manual advises a wait statement in the loop if the condition is incomputable, that is the synthesizer can't determine hen it becomes true, and it's dependent on some signals.
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