Problems with the Ands?

[adytaKriss]

I am new in the programming in VHDL, and am doing a adder subtracter but me mistakes appear with the AND.

1 Library ieee;
2 Use ieee.std_logic_1164.all;
3 Entity Sumador_Restador is
4 port(A0,A1,A2,A3,B0,B1,B2,B3,E: In std_logic;
5 S0,S1,S2,S3,T0,T1,T2,T3,T4: Out std_logic);
6 End Sumador_Restador;
7
8 Architecture sum_res of Sumador_Restador is
9 begin
10 S0 <= B0 XOR E XOR A0 XOR T4;
11 T0 <= B0 XOR E XOR A0 AND T4 OR A0 AND B0 XOR E;
12 S1 <= B1 XOR E XOR A1 XOR T0;
13 T1 <= B1 XOR E XOR A1 AND T0 OR A1 AND B1 XOR E;
14 S2 <= B2 XOR E XOR A2 XOR T1;
15 T2 <= B2 XOR E XOR A2 AND T1 OR A2 AND B2 XOR E;
16 S3 <= B3 XOR E XOR A3 XOR T2;
17 T3 <= B3 XOR E XOR A3 AND T2 OR A3 AND B3 XOR E;
18 T4 <= E AND T3;
19 End sum_res;

sumrestador.vhd (line 11, col 27): (E56) Expected ;, but got AND
Error occurred within 'ARCHITECTURE' at line 8, column 41 in sumrestador.vhd.
sumrestador.vhd (line 11, col 27): (E10) Syntax error at/before reserved symbol 'and'.
sumrestador.vhd (line 13, col 27): (E56) Expected ;, but got AND
sumrestador.vhd (line 13, col 27): (E10) Syntax error at/before reserved symbol 'and'.
sumrestador.vhd (line 15, col 27): (E56) Expected ;, but got AND
sumrestador.vhd (line 15, col 27): (E10) Syntax error at/before reserved symbol 'and'.
sumrestador.vhd (line 17, col 27): (E56) Expected ;, but got AND
sumrestador.vhd (line 17, col 27): (E10) Syntax error at/before reserved symbol 'and'.