PROBLEMS with my PC

[Flueras]

Hello everybody!

I've designed in vhdl a simple 2-phase cl0ck Program Counter(PC) which is described next:
in principle my pc should output the sum of either pc + 1, or Pc + literal (taken from Input3 ), or just the literal(Input3) .

the clk2 is just after the clk1 signal; and have the same period
the control bits mean :
control(3) = enables InOut1 to be input for pc, stored in signal add_in_1
control(2) = enables +1 to be the second input for pc, stored in add_in_2
control(1) = enables Input3 be the second input for pc, stored in add_in_2
those last 2 bits cannot have the same value simultaneous
control(0) = enables the "result" to be outputed


the problem i have is that when i generate the waveform test bench
(for the inputs : control = Dh = 1101b , InOut1 = 5h) it sholud generate at Output2 the value 6h.. but in returns it generates "XXX...X"
for other input values it outputs some "UUU..U"

Could somebody tell me what is wrong with my code?
And suggest some solutions ??


i ve also tried to make the assignments of the add_in_1 and add_in_2 signal inside the process, or
split the process in two : one for each clock... but with no luck !!

entity pc is
Port ( control : in STD_LOGIC_VECTOR (3 downto 0); --controls the inputs and outputs
InOut1 : inout STD_LOGIC_VECTOR (15 downto 0);
clk1 : in STD_LOGIC;
clk2 : in STD_LOGIC;
Input3 : in STD_LOGIC_VECTOR (31 downto 0);
Output2 : out std_logic_vector(15 downto 0));
end pc;

architecture Behavioral of pc is
signal add_in_1, add_in_2, result:std_logic_vector(15 downto 0);

begin

add_in_1 <= InOut1 when control(3) = '1'
else x"0000";

add_in_2 <= x"0001" when control(2 downto 1) = "10"
else Input3(15 downto 0) when control(2 downto 1) = "01"
else x"0000";
process(clk1, clk2, reset)
begin

if clk1 = '1' and clk1'event then
result <= add_in_1 + add_in_2;
end if;

if clk2 = '1' and clk2'event then
if control(0) = '1' then
Output2 <= result;
end if;
InOut1 <= result;
end if;
end process;

end Behavioral;