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Problem with output pin FPGA

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timadria

timadria

Programmer
Dec 12, 2006
1
BE
I'm using an Altera Cyclone FPGA. The software is written in VHDL.
When I simulate the code this works just fine. Even when I program the software into the device.
My project has 1 output. But when I connect this to the other logic on my board the problems start. Now the entire system wont work any more. It seems that this output disturbs al the input pins.
Is there someone that has had the same problem, or can help me whit this ??

Thanks
 
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