Please Check out the following example that explains the problem:
In this example:
variable 'count' = counts the number of positive edges of clock.
variable 'seq_num' = counts the number of sequences ( 1 sequence = 128 bits/positive edges).
After 50 sequences, i have to increment the variable 'delay_val'. This process goes on until 'delay_val' reaches 8 when it has to be reset to 0.
This is what the code is doing. Now, when i simulate this code.... after seq_num reaches 49, it says constant there at 49 because the variable 'count' does not reach 128 after seq_num reaches 49. 'count' increments until 96 and then gets back to zero and the process goes on. The condition for 'seq_num' to increment is that count has to reach 128. Hence, 'seq_num' stays constant at 49. I have no idea why 'count' increments normally for 48 sequences and then stops working well after seq_num reaches 49.
I cannot spot a mistake in the code. I have tried to define 'count' in all possible cases just to be safe. But, apparently it still has a bug.Its highly possible that i might be missing something. I am still an amateur in VHDL coding. I will really appreciate if any one can help me on this.
CODE:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fixedlength is
port(clock,reset,enable : in std_logic;
output : out std_logic;
delay_output : out std_logic;
edge_counter,delay,num_sequence: out integer
);
end fixedlength;
architecture behavioural of fixedlength is
signal new_bit: std_logic;
signal internal_reg: std_logic_vector(10 downto 0);
signal internal_reg_next: std_logic_vector(10 downto 0);
begin
code_gen: process (clock,reset,internal_reg,new_bit)
variable count: integer range 0 to 520;
variable delay_val: integer range 0 to 8;
variable seq_val: integer range 0 to 55;
begin
edge_counter <= count;
delay <= delay_val;
num_sequence <= seq_val;
new_bit <= internal_reg(6) xor internal_reg(5);
output <= internal_reg(0);
delay_output <= internal_reg(0);
internal_reg_next <= internal_reg(9 downto 0) & new_bit;
if (reset = '1') then
internal_reg <= (3 => '1', OTHERS => '0');
count := 0;
delay_val := 0;
seq_val := 0;
elsif (clock'EVENT AND clock ='1') then
if(enable = '1') then
count := count+1;
internal_reg <= internal_reg_next;
if (count = 128) then
seq_val := seq_val+1;
count := 0;
else
count := count;
end if;
if (seq_val = 50) then
count := 0;
delay_val := delay_val+1;
seq_val := 0;
else
count := count;
end if;
if (delay_val = 8) then
delay_val := 0;
count := 0;
else
delay_val := delay_val;
count := count;
end if;
else
internal_reg <= (3 => '1', OTHERS => '0');
count := 0;
end if;
end if;
end process;
end behavioural;