problem with for loop

[fayevalentine]

Hi guys!

This is my issue, I have a module with 8 entries, up to four can be high level, but I do not know which ones, so I use a loop for to look for them, activating the outputs,
this works for me but sinthesizing uses many resources.
(I am using Xilinx software)

Is there a way to do this without using a process?

this is a simple version of my process:

process(ENTRIES)
variable i : integer;
variable j : integer:= 0;
begin
for i in 0 to 7 loop
if ENTRIES(i) = '1' then -- active entry
RESULT(j) <= '1'; --output just 4 maximum
j := j +1;
end if;
end loop;
end process;

Thanks in advance.

 

[blacktom]

fayevalentine,

I tried this piece of code with Altera tools,
but it gives me an empty result.

Maybe Xilinx is working different then?
All I wanted, was to test something because I noticed
that integer J has no range, and is allowed to count to infinity, well actually 2147483647.

This brings a problem because the output RESULT has only
a few bits i presume. So how did Xilinx synhtesise this?

Best regards

 

[fayevalentine]

hi blacktom

this is a part of the Synthesis Report from ISE Foundation:
--------------------------------------------------------------------------
Device utilization summary:
---------------------------

Selected Device : 5vlx85ff676-2 (a Virtex-5 device )


Slice Logic Utilization:
Number of Slice LUTs: 444 out of 51840 0%
Number used as Logic: 444 out of 51840 0%

Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 444
Number with an unused Flip Flop: 444 out of 444 100%
Number with an unused LUT: 0 out of 444 0%
Number of fully used LUT-FF pairs: 0 out of 444 0%
Number of unique control sets: 4

IO Utilization:
Number of IOs: 18
Number of bonded IOBs: 10 out of 440 2%
IOB Flip Flops/Latches: 4

--------------------------------------------------------------------------

ENTRIES is an input port std_logic_vector(7 downto 0)
and RESULT is an output port (3 downto 0)

so I use the for loop to check all entries looking for '1's,
in my design I already consider that up to four entries can be active, so there would be no problem about j variable range, since j=4 is never assigned, although j = 4 gives me a little warning:

WARNING:Xst:790 - "C:/AKROMA/pruebas/pruebas.vhd" line 74: Index value(s) does not match array range.

of course, this is a simple version of my design, actually each entry is a kind of data and RESULT are the addresses.

however I will keep trying a better approach

Thanks in advance.