Hi all.
I have a vhdl module which works fine under behavioural simulation, and even under post-translate simulation. But when I try a post-map simulation, I get the following error:
I have a vhdl module which works fine under behavioural simulation, and even under post-translate simulation. But when I try a post-map simulation, I get the following error:
Code:
# ** Warning: */X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.34 ns; Observed := 0.019 ns; At : 1.2 ns
# Time: 1200 ps Iteration: 2 Instance: /testbench/uut/go_int_2_1392[\code]
The results from the simulation are also wrong (I get a lot of 'X' values). I am using Xilinx ISE 5.2, and Modelsim XE/II starter 5.6e.
Thanks.
Ciarán Hughes