Port map delays signal assignment??

[fsujoe]

I have coded a MAC unit in VHDL as a component and in the simulation the output is valid one clock cycle after the inputs are assigned. However, when I use this component in another file, I assign the inpus to the MAC component and the output isn't assigned until two clocks later..

I port mapped the output signals directly to the the upper level file's output signal. I can't figure out why there is a delay. Any suggestions.

 

[almahtar]

Call me a l33ch, but could I possibly get ahold of that VHDL code? I'd really appreciate it, and perhaps I'd be able to help you solve the problem.