port map and clock

[ghitaion]

Hello . I made a full adder and a register and i want to use them wach time the clock arrives. I don`t know how to do this so i need some help. Problem is in architecture putere.

Best wishes,
GhitaIon.
CODE :

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity putere is
generic ( N : natural := 8);
port(
CLK : in bit;
SOL : out bit_vector( N-1 downto 1)
);
end putere;

--}} End of automatically maintained section

architecture putere of putere is
signal temp : bit_vector ( N-1 downto 1);
signal q : bit;
component FA_1 is
port(A,B,CIN : in bit;
S , COUT : out bit);
end component;

component FA is
generic(N:natural := 8);
port
(
A,B : in bit_vector(N-1 downto 0);
CIN : in bit;
SUM : out bit_vector(N-1 downto 0);
COUT : out bit);
end component;

component REG is
generic (N:natural := 8);
port
(
CLK : in bit;
PL : in bit;
RESET : in bit; -- activ pe 1
SHIFT : in bit;
TO_PUSH : in bit_vector (N-1 downto 0);
REZ : out bit_vector(N-1 downto 0)
);
end component;

begin
SOL <= "00000000";
temp <= SOL;
q <= CLK;
L0 : if q = '1' generate
L1 : REG port map(CLK,'0','0','1',SOL,temp);
end generate;

--L2 : FA port map(SOL,temp,'0',SOL,SOL(N-1) and temp(N-1));
--L3 : FA port map(SOL,"10000000",SOL(N-1) and temp(N-1),SOL,'0');
--L4 : temp <= SOL;

-- enter your statements here --
end putere;