Please help with problem

[megaqujik]

Hi,

what i want to do is simple counter, which switches simple led on board. I can do this with clock on fpga, but if try base that counter on my own clock component it fails.

I enclosed 2 files in the end of post:

top module stereovision,
own clock module videoOutClock


I created 2 processes in top module, first controls LED4 to blink everytime counter_test2 reaches fixed period and second do the same, except it controls LED3. The only difference is that do it on signal v_clock, which is output of entity videoOutClock.

If I replace signal v_clock to CLOCK3( fpga clock) both leds are blinking properly...

Next test i did was to switch on other led when LED3 shoudl switch on too and i succeded - LED2 was enabled, but LED3 was still off...

I work with Xilinx ISE. Test with modelsim all seem to be ok, both leds are blinking.

LED3 is in working order certainly.

Can anyone help?

Regards


topModule:

library ieee;

use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;


entity stereovision is
PORT( CLOCK1, CLOCK3: in std_logic;
BUTTON0, BUTTON1, BUTTON2, BUTTON3 : in std_logic;
LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7 : inout std_logic);
end ;


architecture stereovisionImpl of stereovision is

component videoOutClock
port( CLOCK11: in std_logic;
V_CLOCK, V_DATA_CLOCK: out std_logic);
end component;


signal v_clock: std_logic;
signal v_data_clock : std_logic;


signal counter_test : std_logic_vector(25 downto 0) := "00000000000000000000000000";
signal counter_test2 : std_logic_vector(25 downto 0) :="00000000000000000000000000";

begin
V1: videoOutClock port map (CLOCK3, v_clock, v_data_clock);



jedenrocess(CLOCK3)
begin

if rising_edge(CLOCK3) then
IF counter_test2="10110111000110110000000000" THEN
counter_test2<="00000000000000000000000000";
IF LED4 = '0' THEN
LED4 <='1';
ELSE
LED4 <='0';
END IF;
ELSE
counter_test2 <= counter_test2 + "00000000000000000000000001";
END IF;
end if;

end process;

dwarocess(CLOCK3, v_clock)
begin
if rising_edge(v_clock) then

IF counter_test="10110111000110110000000000" THEN
counter_test<="00000000000000000000000000";
IF LED3 = '0' THEN
LED3 <='1';
ELSE
LED3 <='0';
END IF;
ELSE
counter_test <= counter_test + "00000000000000000000000001";
END IF;
end if;
end process;

end stereovisionImpl;


------------------------------------------------------
videoOutClock module:

library ieee;

use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

-- CLOCK1 - 125MHZ
entity videoOutClock is
port( CLOCK11: in std_logic;
V_CLOCK, V_DATA_CLOCK: out std_logic);
end;


architecture videoOutClockImpl of videoOutClock is
signal counter: std_logic_vector(1 downto 0) := "00";
signal clockState : std_logic := '0';
signal dataClockState : std_logic :='0';

begin

-- co 4ns -> na wyjsiu okres 24ns - 41 mhz
process(CLOCK11)

variable counter_var : integer range 0 to 3;

begin
counter_var := conv_integer(counter);

counter_var := counter_var + 1;

if counter_var = 4 then
counter_var := 0;
clockState <= not clockState;
V_CLOCK <= not clockState;
else
V_CLOCK <= clockState;
end if;


if (counter_var = 1 or counter_var =2) and clockState='1' then
V_DATA_CLOCK <= '1';
else
V_DATA_CLOCK <= '0';
end if;


counter <= conv_std_logic_vector(counter_var, 2);
end process;


end videoOutClockImpl;

 

[Robbe147]

The process in the videoOutClockImpl architecture is a synchronous process, but you forgot to write "if (rising_edge(clk))"

A synchronous process should always look like this:

process(CLOCK11)
begin
if (rising_edge(CLOCK11)) then
...
end if;
end process;

If it was the intention to execute this process both on the rising and falling edge of CLOCK11 (as the simulator will do), you're wrong. Flipflops in an FPGA can store data on rising or falling edges of the clock, but not on both edges.
The synthesis tool will probably see this process as an asynchronous process, and that's why it won't work.

I'm guessing that you're trying to generate a clock with half the frequency of CLOCK3 and a clock that is 90 degrees rotated? If that's the case you better use CoreGen to instantiate a DCM (Digital Clock Manager).