Phase/signal detection

[Kriki]

I tryed to make a program, that detects a signal and clocks it for the rest of the schematic.

So i wanted to ask, if this is a usefull programm or not or what could be done better.

The signal is rectangular and the Master Clock is 4 times of the data signal.

CODE:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;


entity sync is
port( CLK : IN STD_LOGIC;
data : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : buffer STD_LOGIC := '0';
count : buffer integer range 0 to 3;
zdata : buffer STD_LOGIC_VECTOR(3 downto 0);
CLKOUT : buffer STD_LOGIC;
notclk : buffer STD_LOGIC;
DATAOUT : buffer STD_LOGIC

);
END sync;

ARCHITECTURE bdf_type OF sync IS


signal rst : STD_LOGIC;


Begin

process(reset, data)
begin

if(reset = '0')then
ena <= '0';
end if;

if(data'EVENT) then
ena <= '1';
end if;
end process;


PROCESS
BEGIN

WAIT UNTIL CLK'EVENT AND (CLK = '0');

if (ena = '0') then
count <= 0;
end if;

IF (ena = '1') THEN
zdata(3) <= zdata(2);
zdata(2) <= zdata(1);
zdata(1) <= zdata(0);
zdata(0) <= data;
count <= count + 1;

ELSE count <= count;
END IF;
end process;

PROCESS(count, CLK, zdata, ena)
begin

if(count = 0 and (CLK'EVENT and CLK = '1')) then
if(zdata = "1111" or zdata = "0111" or zdata = "1011" or zdata = "1101" or zdata = "1110") then
Dataout <= '1';

elsif (zdata = "0000" or zdata = "1000" or zdata = "0100" or zdata = "0010" or zdata = "0001") then
Dataout <= '0';
end if;
end if;

if ((count mod 2 = 0) and (CLK'EVENT and CLK = '1') and ena = '1') then
if(count = 0) then
CLKOUT <= '1';
else CLKOUT <= '0';
end if;
end if;

end process;


end;


Regards, Kriki