Paramaterizing Arrays via generic mapping??

[gleeion]

I would like to be able to parameterize an I/O port for a component. The problem is that the port in question is an array. I need to be able to vary the number of terms in the array (not the size of the terms).









Is there a way to do this?




(Apart from using a very large bus instead of an array.)









I know the code below is incorrect but it illistrates what I want to do:




(In Bold)







Eg:




COMPONENT node_en IS




GENERIC(n: positive);




PORT(node_IO: INOUT IS ARRAY (n - 1 DOWNTO 0) OF BUS_typ);




END COMPONENT node_en;

 

[SMundschau]

You need to define the array type in a package and then use the new type in your port. Here is a quick example I have compiled. This was done as a single file, but the package can be saves in a file by itself to be used in multiple places as a library. The result after compiling this example was a two dimensional array of pin names such as io_en[2][3]. At least that's how Quartus 2.2 did it.

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

package io_test is
	type bus_type is array (3 downto 0) of std_logic;
	type io_array is array (integer range <>) of bus_type;
end io_test;

library ieee;
use ieee.std_logic_1164.all;
use work.io_test.all;

entity packagetest is
	generic ( N : positive := 6);
	port ( 
		io_en : in io_array( N-1 downto 0 );
		ands : out std_logic_vector( N-1 downto 0)
	);
end entity packagetest;

architecture package_arch of packagetest is
begin
	and_gates : for i in ands'range generate
		gate : process (io_en(i))
			variable vect : bus_type;
			variable a : std_logic;
		begin
			a := '1';
			vect := io_en(i);
			bit : for j in vect'range loop
				a := a and vect(j);
			end loop bit;
			ands(i) <= a;
		end process gate;
	end generate and_gates;
end architecture package_arch;

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