Hello,
Can someone please recommend when to use buffer vs. out mode and when to use packages vs. component instantiation?
I'll be working on a reasonably large project with 2 other students, and we need to get the software engineering aspects of VHDL down pat.
-james
Can someone please recommend when to use buffer vs. out mode and when to use packages vs. component instantiation?
I'll be working on a reasonably large project with 2 other students, and we need to get the software engineering aspects of VHDL down pat.
-james