Hi all,
I'm very new to VHDL n i need some help here.
1) the program sounds like this
package abc is
subtype counter_type is interger range 0 to ((2**13)-1);
constant clock_cycle : counter_type :=8000;
this first lines means my value will go from 0 to 8191, but why the second line means the clock cycle is 8 sec?? i don't understand that.
2) what does
architecture example of abc is
begin
main : process
variable counter : counter_type :=0;
begin
............................. means??
3) how can i implement a wait statement with the following situation.
the traffic light of the main street has to stop when the clock cycle elapsed and there is car on the sideway or there is pedestrian request to cross the road..
THANK YOU SO MUCH!!
Regards,
VHDL noob
I'm very new to VHDL n i need some help here.
1) the program sounds like this
package abc is
subtype counter_type is interger range 0 to ((2**13)-1);
constant clock_cycle : counter_type :=8000;
this first lines means my value will go from 0 to 8191, but why the second line means the clock cycle is 8 sec?? i don't understand that.
2) what does
architecture example of abc is
begin
main : process
variable counter : counter_type :=0;
begin
............................. means??
3) how can i implement a wait statement with the following situation.
the traffic light of the main street has to stop when the clock cycle elapsed and there is car on the sideway or there is pedestrian request to cross the road..
THANK YOU SO MUCH!!
Regards,
VHDL noob