silverhairb
IS-IT--Management
As bandwidth increases and the need for privacy expands, scalable solutions for cryptographic processing will be required. Cryptographic solutions must be capable of handling cryptographic processing at full-bandwidth speeds from the PC through the internet backbone. Current cryptographic processor technology does not address the extreme throughput requirements.
To address these new requirements, new scalable solutions are needed. One method that could easily be implemented to address ultra-high speed throughput is to implement a processor array. This array would process cryptographic blocks in parallel rather than serially, as is the current design. This array would utilize a process scheduler that would assign cryptographic blocks from a data stream to multiple separate processors that would process the blocks in parallel rather. For example, if 48 bytes of data required cryptographic processing using AES (16-byte target block), the data would be divided into 3 blocks and assigned to three different processors. The blocks would be reassembled in the correct sequence after the cryptographic operation. This differs from the current designs using a single processor that would process each block serially.
This type of processing may be applied on packets passing through switches from a source cryptographic scheme to a destination scheme. It may also apply to data being prepared for encrypted storage and for encrypted data being retrieved from storage.
This array processing is algorithm-independent since different algorithms could be loaded to selected processors in the array as needed.
This array scheme is scalable by adding processors to the array to handle a greater number of parallel cryptographic operations.
This array can process multiple messages concurrently by assigning cryptographic operations to unused processors.
This array is suitable for encryption, decryption, translation from one key / encryption scheme to a different key / encryption scheme.
Patent pending (provisional patent issued).
Any thoughts?
[the other] Bill
To address these new requirements, new scalable solutions are needed. One method that could easily be implemented to address ultra-high speed throughput is to implement a processor array. This array would process cryptographic blocks in parallel rather than serially, as is the current design. This array would utilize a process scheduler that would assign cryptographic blocks from a data stream to multiple separate processors that would process the blocks in parallel rather. For example, if 48 bytes of data required cryptographic processing using AES (16-byte target block), the data would be divided into 3 blocks and assigned to three different processors. The blocks would be reassembled in the correct sequence after the cryptographic operation. This differs from the current designs using a single processor that would process each block serially.
This type of processing may be applied on packets passing through switches from a source cryptographic scheme to a destination scheme. It may also apply to data being prepared for encrypted storage and for encrypted data being retrieved from storage.
This array processing is algorithm-independent since different algorithms could be loaded to selected processors in the array as needed.
This array scheme is scalable by adding processors to the array to handle a greater number of parallel cryptographic operations.
This array can process multiple messages concurrently by assigning cryptographic operations to unused processors.
This array is suitable for encryption, decryption, translation from one key / encryption scheme to a different key / encryption scheme.
Patent pending (provisional patent issued).
Any thoughts?
[the other] Bill
