I am pleased to announce the release of the new book a new book "Real Chip Design and Verification Using Verilog and VHDL". You'll find this book very interesting and applicable to current users and as a training book. This is a book that I wished I had when I was doing designs and training. I found during my consulting and training experiences that students of HDLs had more trouble with design concepts than with the HDLs. That book is targeted for current design engineers because it addresses design issues, with HDL as a vehicle for implementation. Book is also intended for users who want to transition into the "other" HDL, and for students of HDLs.
From foreword: "Ben bridges the gaps in a designer's knowledge, he covers the gaps left by other texts ... bridges simulation and synthesis, and this acknowledges that implementation and verification must both be done in design" Synplicity.
"This book is one of the best investments that a logic designer can make" Cadence.
"Real Chip Design and Verification Using Verilog and VHDL", ISBN 0-9705394-2-8
VhdlCohen Publishing, November 2001, 420 pages.
This book addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices expressed in Verilog and VHDL. Topics: 1. Architectural decomposition process; 2. Fundamental elements including synchronous edge detector, counter styles (e.g., Binary, One-Hot, Gray, Johnson), memories (ROM. RAM, FIFO), EDAC, cell primitives and impact on architecture, clocking schemes and PLL; 3. Asynchronous world, metastability, asynchronous FIFO, crossing clock domains; 4. Transaction-based verification methodology, forcing errors, counter and EDAC verification models; 5. Control machines and implementation methodologies with FSM and microprogrammed solutions; 6. Arithmetic machines, HDL Signed and Unsigned types; 7. Mixed mode simulations and synthesis; 8. Minimizing design errors; 9. Verilog/VHDL comparison, Verilog for VHDL users, Verilog coding style guidelines. CD included with lots of goodies.
For book information/purchase see ----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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From foreword: "Ben bridges the gaps in a designer's knowledge, he covers the gaps left by other texts ... bridges simulation and synthesis, and this acknowledges that implementation and verification must both be done in design" Synplicity.
"This book is one of the best investments that a logic designer can make" Cadence.
"Real Chip Design and Verification Using Verilog and VHDL", ISBN 0-9705394-2-8
VhdlCohen Publishing, November 2001, 420 pages.
This book addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices expressed in Verilog and VHDL. Topics: 1. Architectural decomposition process; 2. Fundamental elements including synchronous edge detector, counter styles (e.g., Binary, One-Hot, Gray, Johnson), memories (ROM. RAM, FIFO), EDAC, cell primitives and impact on architecture, clocking schemes and PLL; 3. Asynchronous world, metastability, asynchronous FIFO, crossing clock domains; 4. Transaction-based verification methodology, forcing errors, counter and EDAC verification models; 5. Control machines and implementation methodologies with FSM and microprogrammed solutions; 6. Arithmetic machines, HDL Signed and Unsigned types; 7. Mixed mode simulations and synthesis; 8. Minimizing design errors; 9. Verilog/VHDL comparison, Verilog for VHDL users, Verilog coding style guidelines. CD included with lots of goodies.
For book information/purchase see ----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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