negative integer and vector multiply

[avib]

Hi,
I'm trying to do multiplication between a negative integer and a vector and I'm getting errors
what is wrong with this code (this is only a part of it)
thanks,
Avi

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all ;

ENTITY example IS
PORT(
clk : IN std_logic
);
END example;

ARCHITECTURE arc_example OF example IS

CONSTANT matrix_depth : integer := 3;

subtype matrix_width is std_logic_vector(7 downto 0);
type matrix_type is array (matrix_depth downto 0) of matrix_width;
signal matrix : matrix_type;

subtype multiply_matrix_width is std_logic_vector(15 downto 0);
type multiply_type is array (matrix_depth downto 0) of multiply_matrix_width;
signal multiply : multiply_type;


BEGIN

-- FROM IEEE.NUMERIC_STD:
-- function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of SIZE R'LENGTH before
-- multiplication.

PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
multiply(0) <= ((-1) * matrix(0) );
multiply(1) <= ((-1) * matrix(1) );
multiply(2) <= ((-1) * matrix(2) );
multiply(3) <= ((-1) * matrix(3) );
END IF;
END PROCESS;

END arc_example;


The errors that I receive from Synplicity:

--VHDL syntax check successful!
--Synthesizing work.example.arc_example
--@E:&quot;C:\My Documents\temp.vhd&quot;:36:26:36:40|No matching overload for &quot;*&quot;
--@E:&quot;C:\My Documents\temp.vhd&quot;:37:26:37:40|No matching overload for &quot;*&quot;
--@E:&quot;C:\My Documents\temp.vhd&quot;:38:26:38:40|No matching overload for &quot;*&quot;
--@E:&quot;C:\My Documents\temp.vhd&quot;:39:26:39:40|No matching overload for &quot;*&quot;
--Synthesis failed

 

[RVSachin]

The error indicates that the * operator(for that matter any operator)cannot used on arguments where one is an integer while the other is an user-defined type.

As a work around, convert the second argument to integer, assign it to a signal of integer type. Now convert the product into user-defined type before assigning it to multiply.

 

[avib]

Thanks,
I did that and it works, but I still don't understand why the original code didn't work. Using the numeric_std library should allow multiplying between integer and signed vector:
-- FROM IEEE.NUMERIC_STD:
-- function &quot;*&quot; (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of SIZE R'LENGTH before
-- multiplication.

isn't it?

Avi

 

[RVSachin]

The original code doesn't work because the tool sees matrix(0) as a user-defined type rather than as a signed no. In case you still want your original code to work, then write a function to convert matrix(x) into a signed no., and then the multiplier will work under the package NUMERIC_STD.
---------------------------------------
Try this simple code work which uses NUMERIC_STD

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mult is
port(a: in signed (2 downto 0);
z: out signed (31 downto 0));
end mult;

architecture rtl of mult is
constant b: integer := (-1);
begin
z<= a * b;
end rtl;


RV

 

[avib]

Well, I don't need it right now but it's interesting me:
1. is there any function that converts from STD_LOGIC_VECTOR into SIGNED?
2. I understand that SIGNED uses 2's complement for negative.
How does STD_LOGIC_VECTOR represents negative numbers?
thanks for your help.
Avi