Hi all,
I am working on the Altera Maxplus II Baseline 10.2 software. I have heard that synthesizing a VHDL code in the Maxplus Advanced Synthesizer tool eliminates some errors you might face while compiling it using the 10.2 software.
In fact, this turned out to be true. I had some errors while compiling a code using the Maxplus baseline 10.2 software, but did not have any errors while synthesizing the same code. Now, my question is, how can i simulate my code using the synthesis files i generated ( avoiding compilation using the 10.2 software because this is generating an error) ? There is no simulation tool in the synthesizer and the 10.2 software requires you to compile using the software before simulating.
If any one of you are working on Altera tools, please help me on this.
Thanks
"cinti912"
I am working on the Altera Maxplus II Baseline 10.2 software. I have heard that synthesizing a VHDL code in the Maxplus Advanced Synthesizer tool eliminates some errors you might face while compiling it using the 10.2 software.
In fact, this turned out to be true. I had some errors while compiling a code using the Maxplus baseline 10.2 software, but did not have any errors while synthesizing the same code. Now, my question is, how can i simulate my code using the synthesis files i generated ( avoiding compilation using the 10.2 software because this is generating an error) ? There is no simulation tool in the synthesizer and the 10.2 software requires you to compile using the software before simulating.
If any one of you are working on Altera tools, please help me on this.
Thanks
"cinti912"