Need Help implementing two state machines in vhdl entity

[dd202]

Hi,

please can anyone tell me if the code i have written below is correct and working. it has two state machines. one reads the register and the other writes to the register. should i use signal PIW_Internal or declare a global variable. i understand that the code has little meaning if not combined with all the codes. but any kind of comments or correction necessary will be much appreciated.
thanks
dipayan


library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity PIW_Register is
port ( Write_Reg, clock, reset, PIW_Fetch : in std_logic;
PIW_Acq : in std_logic_vector (23 downto 0);
PIW_Out : out std_logic_vector (23 downto 0);
Reg_Write_Complete : out std_logic;
Reg_Ready : out std_logic);
end entity PIW_Register;

architecture RTL of PIW_Register is
type state_read is (start_read, Read_Register);
type state_write is (start_write, Write_Register);
signal present_state_read, next_state_read : state_read;
signal present_state_write, next_state_write : state_write;
signal PIW_Internal : std_logic_vector (23 downto 0) := x"000000";

begin
seq : process (clock, reset)
begin
if (reset = '1') then
present_state_read <= start_read;
present_state_write <= start_write;
else if rising_edge(clock) then
present_state_read <= next_state_read;
present_state_write <= next_state_write;
end if;
end if;
end process seq;

com_read : process (present_state_read, PIW_Fetch)
begin
Reg_Ready <= '0';
case present_state_read is

when start_read =>
Reg_Ready <= '0';
if (PIW_Fetch = '1') then
next_state_read <= Read_Register;
else next_state_read <= start_read;
end if;

when Read_Register =>
PIW_Out <= PIW_Internal;
Reg_Ready <= '1';
if (PIW_Fetch = '0') then
next_state_read <= start_read;
else next_state_read <= Read_Register;
end if;

end case;
end process com_read;

com_write : process (present_state_write, Write_Reg)
begin
Reg_Write_Complete <= '0';

case present_state_write is

when start_write =>
Reg_Write_Complete <= '0';
if (Write_Reg = '1') then
next_state_write <= Write_Register;
else next_state_write <= start_write;
end if;

when Write_Register =>
PIW_Internal <= PIW_Acq;
Reg_Write_Complete <= '1';
if (Write_Reg = '0') then
next_state_write <= start_write;
else next_state_write <= Write_Register;
end if;

end case;
end process com_write;
end architecture RTL;

 

[jeandelfrigo]

Hi DD202,

At first glance your code should work ok.
I only have one comment.

The signal PIW_Internal is only defind in the case the present_state_write is Write_Register.

I think if you tried synthesis of this peace of code it would give a latch warning.
You should make sure a signal is allways assigned.

A simulator will probably not give any error or warning, but this can lead to very strange behavior.

For the rest I do not see things that are wrong.
Maybe just that it's better to write elsif rather than else if.

In future it might be advisable to add what the problem is you're having with your code. Do you get compile errors, warnings, etc.

Best regards,

Jeandelfrigo