Hello,
I am having troubles with type conversions between integers and std_logic_vectors.
I am using the following libraries :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
When I do :
1 - my_vect <= x"FFFFFFF9";
2 - my_int <= CONV_INTEGER(my_vect);
3 - my_vect <= CONV_STD_LOGIC_VECTOR(my_int, 32);
Where my_vect is a signal of type std_logic_vector(31 downto 0) and my_int is a signal of type integer.
my_vect eventually contains x"FFFFFFF9" which makes sense to me.
But when I try :
1 - my_int <= -7;
2 - my_vect <= CONV_STD_LOGIC_VECTOR(my_int, 32);
The content of my_vect at the end of the calculation is x"00000009" which is not what i am expecting.
I would like the content of my_vect to be x"FFFFFFF9". Does anyone know what i am doing wrong here?
Thanks for your help.
Alexis
I am having troubles with type conversions between integers and std_logic_vectors.
I am using the following libraries :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
When I do :
1 - my_vect <= x"FFFFFFF9";
2 - my_int <= CONV_INTEGER(my_vect);
3 - my_vect <= CONV_STD_LOGIC_VECTOR(my_int, 32);
Where my_vect is a signal of type std_logic_vector(31 downto 0) and my_int is a signal of type integer.
my_vect eventually contains x"FFFFFFF9" which makes sense to me.
But when I try :
1 - my_int <= -7;
2 - my_vect <= CONV_STD_LOGIC_VECTOR(my_int, 32);
The content of my_vect at the end of the calculation is x"00000009" which is not what i am expecting.
I would like the content of my_vect to be x"FFFFFFF9". Does anyone know what i am doing wrong here?
Thanks for your help.
Alexis