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Need help for Integer to std_logic_vector conversion.

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aixil

Programmer
Jul 7, 2003
4
IE
Hello,

I am having troubles with type conversions between integers and std_logic_vectors.
I am using the following libraries :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

When I do :

1 - my_vect <= x&quot;FFFFFFF9&quot;;
2 - my_int <= CONV_INTEGER(my_vect);
3 - my_vect <= CONV_STD_LOGIC_VECTOR(my_int, 32);

Where my_vect is a signal of type std_logic_vector(31 downto 0) and my_int is a signal of type integer.
my_vect eventually contains x&quot;FFFFFFF9&quot; which makes sense to me.

But when I try :

1 - my_int <= -7;
2 - my_vect <= CONV_STD_LOGIC_VECTOR(my_int, 32);

The content of my_vect at the end of the calculation is x&quot;00000009&quot; which is not what i am expecting.

I would like the content of my_vect to be x&quot;FFFFFFF9&quot;. Does anyone know what i am doing wrong here?

Thanks for your help.

Alexis
 
Hi

Your problem may be shown as an example for
&quot;What do we need the f***ing integer for?&quot;
strictly academic arguments.

Why not to keep it all in std_logic_vector and selecting the packages std_logic_signed or std_logic_unsigned for signed/unsigned interpretation of the series of bits?

Or just use signed/unsigned types?

OK
in this particular case, the problem is that you want the result in 2'complement format but the poor std_logic_arith guy does not know about it when you refer to his CONV_STD_LOGIC_VECTOR function with the argument of integer type.

(Me I know that when I see the

use IEEE.STD_LOGIC_SIGNED.ALL;

line, but I am a human not the stupid machine ...)

However you can force him to be more smart asking him first to convert your integer to signed by CONV_SIGNED and then apply the CONV_STD_LOGIC_VECTOR to the signed argument

i.e.

your_vect <= CONV_STD_LOGIC_VECTOR(CONV_SIGNED(your_int, 32),32);

is what i mean

(i would be very surprised if he still refused to cooperate
please let me know then!)

thank you ;)))
 
Hi Berett,

Thank you for your answer. Your solution works.

I still don't understand why the CONV_STD_LOGIC_VECTOR function computes the two's complement only on 4 bits and not on 32 bits ( -7 -> x&quot;00000009&quot; ), but it doesn't really matter.

The reason why I am using integers is that my design performs some arithmetic computations on std_logic_vectors, and use the result as an array index.
I should maybe use ram blocks instead of arrays. I will investigate that when i have time to.

Thx agains for your help,

Alexis
 
You know what?
You are right.
It shall work anyway
and in my comnpiler/simulator
(but this one is very often not compatible with those commonly recognised ones ;(
... it all gives the same, proper result.
- convert_signed, convert_unsigned, convert_slv,
convert(convert) !

(shame)

Sorry for what I have written then. Well it surely holds in the opposite direction - when we convert from std_logic_vector to integer we must get through the convert_signed / convert_unsigned because &quot;as I said&quot;.

Seems like something's wrong with your compiler. Or the reason could be the defined range of integer. Or &quot;your machine&quot; uses different reperesentation of integer values. Not the 2'c but e.g. the sign-module.

Anyway the solution I proposed must work and shall not bring any cost in hardware. If your soft does not accept any other solution ... well

btw if you casually find the reason, please let me know, or name the soft you use

rgds
berett
 
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