Multiplication-Accu into a for not working

[germandj]

Hi guys,
I'm working on a FIR Filter.
On the code above, I'm doing a multiplication (*) of eight signals with a for and with an accumulator I'm doing the addition of every result. The for works to move the pointer of the array.
I've checked several times the code, but on compilation it says that all outputs are stucked to VCC. Why is that? How to solve it?
Without the for it works perfect, but I need it to do severals (*) into a single process..
I'd appreciate any suggestions...
Germán

Library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all; --um die Zahlentyp zu verwechseln
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
use work.coeffiziente.all;

entity mult_accu is
port ( clk_ad: in std_logic;
xn_array, coeff_ein : in reg; --type reg is array(0 to 7) of std_logic_vector (7 downto 0);
sal_accu : out std_logic_vector(7 downto 0)
);
end mult_accu;

architecture arch_mult_accu of mult_accu is

signal data_out_1 : std_logic_vector(13 downto 0);
signal sig_d : std_logic;
signal tmp : std_logic_vector(3 downto 0);
signal dato_ent, coef_ent : std_logic_vector (7 downto 0);
signal sal_mult : std_logic_vector (7 downto 0);
signal accu: std_logic_vector(7 downto 0) ;
signal reg_sal_mult : reg;

begin

-- MULTIPLICATOR and ACCUMULATOR --
MUL: process

begin

wait until rising_edge(clk_ad);

for tmp in 0 to 7 loop

dato_ent <= xn_array(tmp);
coef_ent <= coeff_ein(tmp);

sig_d <= dato_ent(7) xor coef_ent(7);
data_out_1 <= std_logic_vector(unsigned(dato_ent(6 downto 0))*unsigned(coef_ent(6 downto 0)));

if sig_d='1' then
if data_out_1(13 downto 7)=0 then
sal_mult(7 downto 0) <= (&quot;00000000&quot;
else sal_mult(6 downto 0)<= data_out_1(13 downto 7);
sal_mult(7) <= sig_d;
end if;
else sal_mult(6 downto 0) <= data_out_1(13 downto 7);
sal_mult(7) <= sig_d;
end if;

--ACCUMULATOR

accu <= sal_mult + accu;

end loop;
--End of for. Accu is ready

sal_accu <= accu;

end process MUL;

end arch_mult_accu;