Multiplexing (almost ready)

[johan1981]

Hi,

We have to built a program that controls 3 7seg-displays. The displays needs to be controlled by multiplexing.
The program has to show combinations of NNW, NNE, SW, W, etc. (all wind directions)

We use the Cypress CY37064P44-125JC.

We have built a code which works fine, but the multiplexing doesn't....only 1 display works.

Is there someone that can help us, to activat all displays by multiplexing.

(excuse us for bad english)

The code is shown below:

---------------------------------------------------------------------------
-- This Vhdl file is generated by EASE/HDL from TRANSLOGIC BV,
-- the 'Graphical Systems Design Tool' tool.
--
-- Ease Version 4.0 (Revision 6).
-- Time stamp : Fri Jun 03 14:04:21 2005.
--
-- Designed by : .
-- Company : .
-- Design info : .
---------------------------------------------------------------------------

---------------------------------------------------------------------------
-- Entity declaration of 'disp4_muxed'.
---------------------------------------------------------------------------


---------------------------------------------------------------------------
-- Architecture 'a0' of 'disp4_muxed'
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;



ENTITY disp4_muxed IS
PORT ( clk_ref : IN std_logic;
sys_rst : IN std_logic;
data_in : IN std_logic_vector ( 3 downto 0);
gate0 : OUT std_logic;
gate1 : OUT std_logic;
gate2 : OUT std_logic;
digit_out: OUT std_logic_vector (6 downto 0) -- MSB=g, f, e, .., LSB=a
);

attribute pin_numbers of disp4_muxed: entity is
"clk_ref:35 " &
"sys_rst:36 " &
"data_in(3):40 " &
"data_in(2):41 " &
"data_in(1):42 " &
"data_in(0):43 " &
"gate0:26 " &
"gate1:24 " &
"gate2:25 " &
"digit_out(6):2 " &
"digit_out(5):3 " &
"digit_out(4):19 " &
"digit_out(3):18 " &
"digit_out(2):17 " &
"digit_out(1):5 " &
"digit_out(0):4 ";

END disp4_muxed;

architecture a0 of disp4_muxed is
TYPE allowed_seg_states IS (seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g);
TYPE allowed_digit_states IS (digit_1, digit_2, digit_3);
SIGNAL state_seg : allowed_seg_states;
SIGNAL state_digit : allowed_digit_states;
SIGNAL indata : std_logic_vector (3 downto 0);
CONSTANT LOW : std_logic := '0';
CONSTANT HIGH : std_logic := '1';

BEGIN

data_in_latch : PROCESS (sys_rst, clk_ref)
BEGIN
IF (sys_rst=HIGH) THEN
indata <= "0000";
ELSIF (clk_ref=HIGH and clk_ref'EVENT) THEN
indata <= data_in;
END IF;

END PROCESS data_in_latch;



DIGIT_SM : PROCESS (sys_rst, clk_ref)
VARIABLE digit_state : allowed_digit_states;
BEGIN
IF (sys_rst=HIGH) THEN
digit_state := digit_1;
ELSIF (clk_ref=HIGH and clk_ref'EVENT) THEN
CASE (digit_state) IS
WHEN digit_1 =>
IF (state_seg = seg_g) THEN digit_state := digit_2; END IF;
WHEN digit_2 =>
IF (state_seg = seg_g) THEN digit_state := digit_3; END IF;
WHEN digit_3 =>
IF (state_seg = seg_g) THEN digit_state := digit_1; END IF;
END CASE;
END IF;
state_digit <= digit_state;
END PROCESS DIGIT_SM;


digit_decode : PROCESS (state_digit, indata)
VARIABLE segments : std_logic_vector (6 downto 0);
VARIABLE gates : std_logic_vector (2 downto 0);
BEGIN
gates := "000";
CASE (state_digit) IS
WHEN digit_1 =>
gates := "100";
case (indata) is
when "0000" => segments := "0110111";
when "0001" => segments := "0110111";
when "0010" => segments := "0110111";
when "0011" => segments := "0111111";
when "0100" => segments := "0111111";
when "0101" => segments := "0111111";
when "0110" => segments := "1011011";
when "0111" => segments := "1011011";
when "1000" => segments := "1011011";
when "1001" => segments := "1011011";
when "1010" => segments := "1011011";
when "1011" => segments := "0111110";
when "1100" => segments := "0111110";
when "1101" => segments := "0111110";
when "1110" => segments := "0110111";
when "1111" => segments := "0110111";
when others => segments := "1000000";
end case;
WHEN digit_2 =>
gates := "010";
case (indata) is
when "0000" => segments := "0000000";
when "0001" => segments := "0110111";
when "0010" => segments := "0111111";
when "0011" => segments := "0110111";
when "0100" => segments := "0000000";
when "0101" => segments := "1011011";
when "0110" => segments := "0111111";
when "0111" => segments := "1011011";
when "1000" => segments := "0000000";
when "1001" => segments := "1011011";
when "1010" => segments := "0111110";
when "1011" => segments := "1011011";
when "1100" => segments := "0000000";
when "1101" => segments := "0110111";
when "1110" => segments := "0111110";
when "1111" => segments := "0110111";
when others => segments := "1000000";
end case;
WHEN digit_3 =>
gates := "001";
case (indata) is
when "0000" => segments := "0000000";
when "0001" => segments := "0111111";
when "0010" => segments := "0000000";
when "0011" => segments := "0111111";
when "0100" => segments := "0000000";
when "0101" => segments := "0111111";
when "0110" => segments := "0000000";
when "0111" => segments := "0111111";
when "1000" => segments := "0000000";
when "1001" => segments := "0111110";
when "1010" => segments := "0000000";
when "1011" => segments := "0111110";
when "1100" => segments := "0000000";
when "1101" => segments := "0111110";
when "1110" => segments := "0000000";
when "1111" => segments := "0111110";
when others => segments := "1000000";
END CASE;
end case;
digit_out <= segments;
gate0 <= gates(2);
gate1 <= gates(1);
gate2 <= gates(0);

END PROCESS digit_decode;


PROCESS (clk_ref, sys_rst)
VARIABLE seg_state : allowed_seg_states;
BEGIN
IF (sys_rst=HIGH) THEN
seg_state := seg_a;
ELSIF (clk_ref=HIGH AND clk_ref'EVENT) THEN
CASE (seg_state) IS
WHEN seg_a =>
seg_state := seg_b;
WHEN seg_b =>
seg_state := seg_c;
WHEN seg_c =>
seg_state := seg_d;
WHEN seg_d =>
seg_state := seg_e;
WHEN seg_e =>
seg_state := seg_f;
WHEN seg_f =>
seg_state := seg_g;
WHEN seg_g =>
seg_state := seg_a;

END CASE;
END IF;
state_seg <= seg_state;
END PROCESS;

end a0 ; -- of disp4_muxed

 

[vhdllearner]

if you dont mind my asking... how exactly do you display N and W on the 7 segment displays? when, for instance, the wind direction is north, then how is it displayed? " N ", "-N-", etc?

 

[vhdllearner]

ok... well i have no idea if this actually works or not... as my compiler does not recognise the command 'pin_numbers', so i can't simulate it and i dont have the resources to actually make it. since you have tried this already, im assuming yours does accept the command, so i wont bother changing that.

it seemed to me that the problem with your program was that last process... scrolling through segments... but i couldnt actually see that it did anything, so i got rid of it! as with the scrolling through displays...

oh yeah, and i got rid of that clk_ref as well, as it just wasnt necessary. if you really want it, then its easy to add back in but it is really just adding usless complication i would have thought. it will also make your circuit smaller, surely?

do bear in mind that im a beginner tho, so perhaps it just went right over my head. i only actually started learning vhdl this week. i just thought that this might be some interesting practise.

so if anyone else can look over this code, then that would be much appreciated... would love some feedback!!

anyways... here goes...!
p.s. i hope you can read it ok. i think it will lose all of the tabs that i put in. but oh well.



-- NOTE:
-- now, no clk_ref required. sys_rst rising edge = reset. falling edge = load data_in.
-- ***********************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY disp4_muxed IS
PORT ( sys_rst : IN std_logic;
data_in : IN std_logic_vector (3 downto 0);
gates_out : OUT std_logic_vector (2 downto 0); -- MSB = display 3... LSB = display 1 (com)
digit_out : OUT std_logic_vector (6 downto 0)); -- MSB=g, f, e, .., LSB=a
-- where: (going across)
-- _ a
-- |_| f, g, b
-- |_|. e, d, c

attribute pin_numbers of disp4_muxed: entity is
"sys_rst:36 " &
"data_in(3):40 " &
"data_in(2):41 " &
"data_in(1):42 " &
"data_in(0):43 " &
"gates_out(0):26 " &
"gates_out(1):24 " &
"gates_out(2):25 " &
"digit_out(6):2 " &
"digit_out(5):3 " &
"digit_out(4):19 " &
"digit_out(3):18 " &
"digit_out(2):17 " &
"digit_out(1):5 " &
"digit_out(0):4 ";

END disp4_muxed;

architecture a0 of disp4_muxed is
SIGNAL indata : std_logic_vector (3 downto 0);
CONSTANT LOW : std_logic := '0';
CONSTANT HIGH : std_logic := '1';
BEGIN

-- CHECK TO SEE IF PROGRAM IS TO BE RESET
reset_now : PROCESS (sys_rst)
BEGIN
IF (sys_rst=HIGH and sys_rst'event) THEN
indata <= "UUUU";
end if;
end process reset_now;

-- CHECK WHETHER TO LOAD DATA
data_in_latch: PROCESS (sys_rst)
BEGIN
IF (sys_rst=LOW and sys_rst'event) THEN
indata <= data_in;
END IF;
END PROCESS data_in_latch;

-- OUTPUT DATA TO DISPLAYS
display_digits : PROCESS
VARIABLE segments : std_logic_vector (6 downto 0);
VARIABLE gates : std_logic_vector (2 downto 0);
BEGIN
gates := "001";
CASE (indata) is
when "0000" => segments := "0110111"; -- n -- you will probably want to change all of
-- these values... from here onwards.
when "0001" => segments := "0110111"; --n
when "0010" => segments := "0110111"; --n
when "0011" => segments := "0110111"; --n
when "0100" => segments := "1111001"; --e
when "0101" => segments := "1111001"; --e
when "0110" => segments := "1111001"; --e
when "0111" => segments := "1111001"; --e
when "1000" => segments := "1101101"; --s
when "1001" => segments := "1101101"; --s
when "1010" => segments := "1101101"; --s
when "1011" => segments := "1101101"; --s
when "1100" => segments := "0111110"; --w
when "1101" => segments := "0111110"; --w
when "1110" => segments := "0111110"; --w
when "1111" => segments := "0111110"; --w
when others => segments := "1000000";
end case;

digit_out <= segments;
gates_out <= gates;
wait for 10 ns; -- this value has not been tested. it may require
-- longer to illuminate the LEDs?!

gates := "010";
CASE (indata) is
when "0000" => segments := "0000000";
when "0001" => segments := "0110111"; --n
when "0010" => segments := "1111001"; --e
when "0011" => segments := "1111001"; --e
when "0100" => segments := "0000000";
when "0101" => segments := "1111001"; --e
when "0110" => segments := "1111001"; --e
when "0111" => segments := "1101101"; --s
when "1000" => segments := "0000000";
when "1001" => segments := "1101101"; --s
when "1010" => segments := "0111110"; --w
when "1011" => segments := "0111110"; --w
when "1100" => segments := "0000000";
when "1101" => segments := "0111110"; --w
when "1110" => segments := "0111110"; --w
when "1111" => segments := "0110111"; --n
when others => segments := "1000000";
end case;

digit_out <= segments;
gates_out <= gates;
wait for 10 ns;

gates := "100";
CASE (indata) is
when "0000" => segments := "0000000";
when "0001" => segments := "1111001"; --e
when "0010" => segments := "0000000";
when "0011" => segments := "1111001"; --e
when "0100" => segments := "0000000";
when "0101" => segments := "1111001"; --e
when "0110" => segments := "0000000";
when "0111" => segments := "1111001"; --e
when "1000" => segments := "0000000";
when "1001" => segments := "0111110"; --w
when "1010" => segments := "0000000";
when "1011" => segments := "0111110"; --w
when "1100" => segments := "0000000";
when "1101" => segments := "0111110"; --w
when "1110" => segments := "0000000";
when "1111" => segments := "0111110"; --w
when others => segments := "1000000";
end case;

digit_out <= segments;
gates_out <= gates;
wait for 10 ns;

END PROCESS display_digits;

end a0; -- of disp4_muxed