multiple rising edges(clocks), falling edge

[tassingremi]

Hi all,
i would really appreciate to get some help here.

Basically, i have a component with 3 inputs(buttons) and i need to check if any of them has been pressed or released for further use. So i wanted to deal with them as they were just clocks. But it seems like multiple clocks are not supported in VHDL.

Is it there any way to overcome this problem?
I saw this post:

http://www.tek-tips.com/gviewthread.cfm/lev2/4/lev3/32/pid/284/qid/233492

but it didn't have any satisfaying solution, so falling edge still a nightmare for me since i want to check rising and falling edge seperately and for different "clocks".

It's really urgent, help P-L-E-A-S-E!

 

[tassingremi]

I try using multiple architectures for the same entity but still don't if it will work.

 

[avib]

hi,
if you have a clock in your design then you can detect rising and falling edges by synchronising these signals to the clocks and using one or two (if you want to be sure that you're not sampling noises) Flip Flops and comparing the input signal and the output of the Flip Flop

example:

entity ...
port(
a : in std_logic
);

architecture ...

signal a1 : std_logic;

begin

process(clk)
begin
if clk'event and clk = '1' then
a1 <= a;
if a = '0' and a1 = '1' then -- falling edge detection
-- .......
end if;
-- or
if a = '1' and a1 = '0' then -- rising edge detection
-- .......
end if;
end if;
end process;

 

[tassingremi]

yeah!
That's what i did.
thanx anyway.
The multiple architectures stuff didn't work because the compiler was only considering the last one.