This is the first time I put multiple entities in one file... and I get an error. This is the code:
entity sbox1 is
PORT(
sel: in std_logic_vector(0 to 5);
retval: out std_logic_vector(0 to 3)
);
end sbox1;
entity sbox2 is
PORT(
sel: in std_logic_vector(0 to 5);
retval: out std_logic_vector(0 to 3)
);
end sbox2;
architecture Behavioral of sbox1 is
begin
-- bunch of code
end Behavioral;
architecture Behavioral of sbox2 is
begin
-- bunch of code
end Behavioral;
If I remove sbox2 from the code, everything goes fine. If I remove sbox1, everything goes fine too. BUT, if I try to complie the above code, Xilinx Project Navigator 7.1 says:
ERROR:HDLParsers:3312 (...) Undefined symbol 'std_logic_vector'.
ERROR:HDLParsers:1209 (...) std_logic_vector: Undefined symbol (last report in this block)
How come?
entity sbox1 is
PORT(
sel: in std_logic_vector(0 to 5);
retval: out std_logic_vector(0 to 3)
);
end sbox1;
entity sbox2 is
PORT(
sel: in std_logic_vector(0 to 5);
retval: out std_logic_vector(0 to 3)
);
end sbox2;
architecture Behavioral of sbox1 is
begin
-- bunch of code
end Behavioral;
architecture Behavioral of sbox2 is
begin
-- bunch of code
end Behavioral;
If I remove sbox2 from the code, everything goes fine. If I remove sbox1, everything goes fine too. BUT, if I try to complie the above code, Xilinx Project Navigator 7.1 says:
ERROR:HDLParsers:3312 (...) Undefined symbol 'std_logic_vector'.
ERROR:HDLParsers:1209 (...) std_logic_vector: Undefined symbol (last report in this block)
How come?