multiple clocks

[vitalsys]

I am trying to implement a counter that will inc. or dec. based on 2 clock sources. the following is the simplified code. CLK_A and CLK_B are 90 degrees out of phase.
I am getting the error "Signal Q_IN cannot be synthesized, bad synchronous description". using xilinx webpack 6.1.03i. will greatly appreciate any help.

thanks in advance,
Abdul Rafiq




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CounterScaler is

port ( CLEAR, CLK_A, CLK_B: in std_logic;
Q : out std_logic_vector(7 downto 0));

end CounterScaler;

architecture Behavioral of CounterScaler is
signal Q_IN : std_logic_vector(7 downto 0);
begin
Q <= Q_IN;
process( CLK_A, CLK_B, CLEAR )
begin

if CLEAR='1' then
Q_IN <= "00000000";

if rising_edge(CLK_A) and CLK_B = '0' then
q_in <= q_in + '1';

elsif rising_edge(CLK_B) and CLK_A = '1' then
q_in <= q_in - '1';

END IF;

end process;

end Behavioral;

 

[VHDLguy]

You can only have one rising edge (or wait) statement per process.

Try to think about what you are creating there. flip-flop's with two clocks. No such flip-flop exists.

depending on the relationship between your two clocks you could create some kind of rising edge detection that feeds into one flip flop (well one group of flip-flops since its a multi-bit counter).

What I don't understand is your description of the clocks. You mention that they are 90 degrees out of phase.... if so then you won't really have a counter since it will go from 0 to 1 and back to 0 all the time. I suspect that if you are using these signals to count, then maybe they are not clocks, maybe strobes would be a better description? (you have just tried to implement them as a strobe to the clock input of a flip-flop)


Can you give a better description of the 'clocks'? and any other system clocks that you have that we might find useful to create this circuit another way.

Also, your first if rising edge should be an elsif.
Without the second rising edge statement that would create an asyncronous clear (or reset) to your flip-flop.

--

http://www.lateralsands.com/

 

[amitsdsu]

hi there
hey i have the same problem with my vhdl code. I understand how the flip flops work and that only one clock can manage that but suppose

i have an input and 1 ff will enable or disable it according to the clock1

after that the output of that ff would go to a combinatorial block and then probably i would let it go to other module by a flipflop which is controlled by other clock

if it doesnt make sense plz explain me it would be great help

amit

 

[AllEars]

Hi, vitalsys:

I went through a similar designe coping with A-B signals 10 years ago, not using VHDL then. I think I understand your application well. Here is my solution to your problem. I did the synthesis and post-layout simulation and proved it works. The design consists 5 entities, the top counter is what you need, 4 other entities are sub-components to be used inside the top one.

-- cnt1 file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity CNT1 is
port(
CLR : in std_logic;
CLK_A : in std_logic;
CLK_B : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end entity CNT1;

architecture Behaviour of CNT1 is
signal Q_IN : std_logic_vector(7 downto 0);
begin
Q <= Q_IN;
process( CLR, CLK_A )
begin
if CLR='1' then
Q_IN <= (others=>'0');
elsif rising_edge( CLK_A ) then
if CLK_B='0' then
Q_IN <= Q_IN+'1';
else
Q_IN <= Q_IN-'1';
end if;
end if;
end process;
end architecture Behaviour;

-- cnt2 file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity CNT2 is
port(
CLR : in std_logic;
CLK_A : in std_logic;
CLK_B : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end entity CNT2;

architecture Behaviour of CNT2 is
signal Q_IN : std_logic_vector(7 downto 0);
begin
Q <= Q_IN;
process( CLR, CLK_A )
begin
if CLR='1' then
Q_IN <= (others=>'0');
elsif falling_edge( CLK_A ) then
if CLK_B='0' then
Q_IN <= Q_IN-'1';
else
Q_IN <= Q_IN+'1';
end if;
end if;
end process;
end architecture Behaviour;

-- cnt3 file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity CNT3 is
port(
CLR : in std_logic;
CLK_A : in std_logic;
CLK_B : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end entity CNT3;

architecture Behaviour of CNT3 is
signal Q_IN : std_logic_vector(7 downto 0);
begin
Q <= Q_IN;
process( CLR, CLK_B )
begin
if CLR='1' then
Q_IN <= (others=>'0');
elsif falling_edge( CLK_B ) then
if CLK_A='0' then
Q_IN <= Q_IN+'1';
else
Q_IN <= Q_IN-'1';
end if;
end if;
end process;
end architecture Behaviour;

-- cnt4 file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity CNT4 is
port(
CLR : in std_logic;
CLK_A : in std_logic;
CLK_B : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end entity CNT4;

architecture Behaviour of CNT4 is
signal Q_IN : std_logic_vector(7 downto 0);
begin
Q <= Q_IN;
process( CLR, CLK_B )
begin
if CLR='1' then
Q_IN <= (others=>'0');
elsif rising_edge( CLK_B ) then
if CLK_A='1' then
Q_IN <= Q_IN+'1';
else
Q_IN <= Q_IN-'1';
end if;
end if;
end process;
end architecture Behaviour;

-- top cnt file
entity CounterScaler is
port(
CLR : in std_logic;
CLK_A : in std_logic;
CLK_B : in std_logic;
Q : out std_logic_vector( 7 downto 0 )
);
end entity CounterScaler;

architecture Behaviour of CounterScaler is

signal Q1 : std_logic_vector( 7 downto 0 );
signal Q2 : std_logic_vector( 7 downto 0 );
signal Q3 : std_logic_vector( 7 downto 0 );
signal Q4 : std_logic_vector( 7 downto 0 );

component CNT1 is
port(
CLR : in std_logic;
CLK_A : in std_logic;
CLK_B : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end component CNT1;

component CNT2 is
port(
CLR : in std_logic;
CLK_A : in std_logic;
CLK_B : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end component CNT2;

component CNT3 is
port(
CLR : in std_logic;
CLK_A : in std_logic;
CLK_B : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end component CNT3;

component CNT4 is
port(
CLR : in std_logic;
CLK_A : in std_logic;
CLK_B : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end component CNT4;

begin

Q <= Q1 + Q2 + Q3 + Q4;

C1 : CNT1 port map(CLR=>CLR, CLK_A=>CLK_A, CLK_B=>CLK_B, Q=>Q1);
C2 : CNT2 port map(CLR=>CLR, CLK_A=>CLK_A, CLK_B=>CLK_B, Q=>Q2);
C3 : CNT3 port map(CLR=>CLR, CLK_A=>CLK_A, CLK_B=>CLK_B, Q=>Q3);
C4 : CNT4 port map(CLR=>CLR, CLK_A=>CLK_A, CLK_B=>CLK_B, Q=>Q4);

end architecture Behaviour;

Good luck with your project.

 

[VHDLguy]

amitsdsu
Sure you can do that if you want. However in order to do so you must create multiple processes. One for you falling edge signal and another for your rising edge signal. Then a final process, or just some logic to create your resulting signal.

You must stick to these rules:
1. Only one wait statement, event etc per process
2. any signal must only be driven from one signal

the caveat on 2. is that you can have multiple drivers (for some logic types) as long as all drivers are high-impedance and only one driver is driving at a particular time.

--

http://www.lateralsands.com/

 

[VHDLguy]

oops 2 should read.
2. any signal must only be driven from one process

--

http://www.lateralsands.com/

 

[cavern]

im using an lattice ispMach 4000 device 64/32

I cannot add Q1 + Q2 + Q3 + Q4. My vector are 16 bits wide and i got this error:

The number of clusters, 72 , that are required to
implement the design exceeds the number, 64 , of clusters available in the device.

Number of macrocells required, 65 , exceeds the device
limit of 64 cells.

This error is really caused by that addition..

how can i solved that problem?

 

[gordwait]

I'm fairly certain that the Xilinx device does not have a flip flop element that has two separate clock inputs, and as well, this is not a common operation in any hardware, so the synthesis tools do not know how to create what you are after.

The trick with hardware languages is to create a block diagram of real hardware components that are available to you, then force the language to describe it.

VHDL and other languages can model all sorts of behavior that is not available in real hardware, and so the synthesis tool can only spit out an error when fed the description.

How would you describe a two clocked counter if restricted to off the shelf TTL logic (flipflops, nand, nor gates etc)?
Cheers,
Gord Wait

 

[jeandelfrigo]

Cavern,

I'm not familiar with lattice devices but it seems to me that either you get a larger device (more logical cells) or you should limit your buswidth.

Gordwait,

I agree with you although making a diagram of a complex design with primitives (FFs, muxes, gates) can be quit impossible to do.
So for smaller less complex designs it is possible.

Also I would advise reading the device datasheet before you start coding or even before you make a device selection. Most datsheet give a fairly good idea on what and how many primitive ressources are available in the device.


regards

jeandelfrigo