Modelsim compilation trouble 1

[alvaroalo]

Hi

I need to design an ALU with adders. I have the following code, which I think is right, but modelsim launch me three errors in lines of add0, add1, add2, add3 and add4 (the three errors in each line).


"Cannot read output 's'"
"Prefix of indexed name must be an array"
"Statement cannot be labeled"

I don't know which could be the trouble
Please, help me!!!

The code is the following:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY sumador5bits IS
PORT ( X: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
Y: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
Cin: IN STD_LOGIC;
S: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
Cout: OUT STD_LOGIC);
END sumador5bits;

ARCHITECTURE sum5 OF sumador5bits IS

signal caux: STD_LOGIC_VECTOR (3 DOWNTO 0);

COMPONENT sumador

PORT ( X: IN STD_LOGIC;
Y: IN STD_LOGIC;
Cin: IN STD_LOGIC;
S: OUT STD_LOGIC;
Cout: OUT STD_LOGIC);

END COMPONENT;

BEGIN

sumad0:sumador (X(0),Y(0),Cin,S(0),caux(0));
sumad1:sumador (X(1),Y(1),caux(0),S(1),caux(1));
sumad2:sumador (X(2),Y(2),caux(1),S(2),caux(2));
sumad3:sumador (X(3),Y(3),caux(2),S(3),caux(3));
sumad4:sumador (X(4),Y(4),caux(3),S(2),Cout);

END sum5;


Thanks!!!

 

[BertVhdl]

Hi Alvaroalo!

The sumad0 to 5 aren't recognized as a component, but as a statement. Try the following:

sumad0:sumador port map(X(0),Y(0),Cin,S(0),caux(0));

You forgot the "port map"

 

[alvaroalo]

Thank you, Bert Broer!!!
I found finally the mistake, but thank you anyway!!!