ModelSim/bidirectional Ports

[IKP]

Hello,
i'm new in VHDL and in simulation with ModelSim and it is the first time that i post something to a forum.
I have a problem to simulate in ModelSim InOut Ports:

For example:

process(clk1)
begin
if clk1'event and clk1='1' then
if wrreq='1' then temp<=R;
elsif rdreq='1' then R<=x&quot;1111&quot;;
end if;
end if;
end process;

When I simluate this little process, I get in the WaveForm a red unknown X for the InOut Port R.
The simulation .do file is also only a little test file:

process
begin
wait for 100 ns;
--wrreq
R<=x&quot;5555&quot;;
wrreq<='1';
rdreq<='0';
wait for 100 ns;
wrreq<='0';
rdreq<='0';
wait for 150 ns;
--rdreq
wrreq<='0';
rdreq<='1';
wait for 150 ns;
wrreq<='0';
rdreq<='0';
wait;
end process;

Perhaps someone has an idea and can help me.
Thank you.
Chris

 

[senjed]

Hi
it's simple. you are driving the port R both in the testbench and in the inner process. When you intend just one of these you should assign it all z (others =< 'Z')in the other statement. (for example when you want to read from this port, do this in the testbench)

 

[senjed]

Hi
It's very simple. You are driving a signal both in your testbench and in the process in the core. That always will cause congestion and so results in X's. Solution is simple too. When in one of the two statements is to be perofrormed, (and the other is of course not to be active at the same time), try assigning the other one (otehrs => 'Z'). It means to High-Z the signal and allow any other source to drive it. for example when you're to read use in the testbench:
--rdreq
wrreq<='0';
rdreq<='1';
R <= (others => 'Z');
...

 

[IKP]

Thank you for the explanation. That was the correct tip.Now I can simulate it with modelsim.
Chris