minimize logic

[meganwhite]

Hi guys I need some help to minimize the logic in my code in order to fit it in the fpga.

Basically what the code does is as follows:

From a 32 byte input data I have to retrieve 112 bits and transmit them serially.

the code is

lib.....
ieee....
entity...
port(
...
Data_1 : in std_logic_vector(7 downto 0);
...
...
end entity

architecture ...is

type bytemem is array(31 downto 0) of std_logic_vector(7 downto 0);

signal...
...
signal dt_tmp : bytemem;
signal a_28 : std_logic_vector(27 downto 0);
signal b_28 : std_logic_vector(27 downto 0);
signal c_28 : std_logic_vector(27 downto 0);
signal d_28 : std_logic_vector(27 downto 0);
signal addr : std_logic_vector(5 downto 0);

begin

process(clk1, rst, fifowt, addr)
begin

if (rst = '1') then
addr <= &quot;000000&quot;;
dt_tmp <= (others => x&quot;00&quot;

elsif falling_edge(clk1) then
if (fifowt = '1' ) then
dt_tmp(conv_integer(addr)) <= data_1;
addr <= addr + 1;
end if;
if (addr = X&quot;1F&quot then

addr <= &quot;000000&quot;;

end if;
end if;
end process;


-- I need to throw away some bytes but need a few bits from --these(LSB's)

temp0 <= dt_tmp(0);
temp1 <= dt_tmp(4);
temp2 <= dt_tmp(8);
temp3 <= dt_tmp(12);
temp4 <= dt_tmp(16);
temp5 <= dt_tmp(20);
temp6 <= dt_tmp(24);
temp7 <= dt_tmp(28);


process(rst, clk1, ctr)
begin

if (rst = '1' or ctr = '0') then

a_28 <= X&quot;0000000&quot;;
b_28 <= X&quot;0000000&quot;;
c_28 <= X&quot;0000000&quot;;
d_28 <= X&quot;0000000&quot;;

elsif rising_edge(clk1) then
if (temp0(6) = '1')then

a_28 (27 downto 20) <= dt_tmp(1);
a_28 (19 downto 12) <= dt_tmp(2);
a_28 (11 downto 4) <= dt_tmp(3);
a_28 (3 downto 1) <= temp0(2 downto 0);
a_28 (0) <= oddp0; -- Odd parity bit

-- if (temp1(6) = '1') then

b_28 (27 downto 20) <= dt_tmp(5);
b_28 (19 downto 12) <= dt_tmp(6);
b_28 (11 downto 4) <= dt_tmp(7);
b_28 (3 downto 1) <= temp1(2 downto 0);
b_28 (0) <= oddp1; -- Odd parity bit

--if (temp2(6) = '1') then

c_28 (27 downto 20) <= dt_tmp(9);
c_28 (19 downto 12) <= dt_tmp(10);
c_28 (11 downto 4) <= dt_tmp(11);
c_28 28(3 downto 1) <= temp2(2 downto 0);
c_28 (0) <= oddp2; -- Odd parity bit

-- if (temp4(6) = '1') then

d_28 (27 downto 20) <= dt_tmp(17);
d_28 (19 downto 12) <= dt_tmp(18);
d_28 (11 downto 4) <= dt_tmp(19);
d_28 (3 downto 1) <= temp4(2 downto 0);
d_28 (0) <= oddp3; -- Odd parity bit






elsif (temp0(6) = '0')then

d_28 (27 downto 20) <= dt_tmp(1);
d_28 (19 downto 12) <= dt_tmp(2);
d_28 (11 downto 4) <= dt_tmp(3);
d_28 (3 downto 1) <= temp0(2 downto 0);
d_28 (0) <= oddp3; -- Odd parity bit

--if (temp4(6) = '0') then

a_28 (27 downto 20) <= dt_tmp(17);
a_28 (19 downto 12) <= dt_tmp(18);
a_28 (11 downto 4) <= dt_tmp(19);
a_28 (3 downto 1) <= temp4(2 downto 0);
a_28 (0) <= oddp0; -- Odd parity bit

-- if (temp5(6) = '0') then

b_28 (27 downto 20) <= dt_tmp(21);
b_28 (19 downto 12) <= dt_tmp(22);
b_28 (11 downto 4) <= dt_tmp(23);
b_28 (3 downto 1) <= temp5(2 downto 0);
b_28 (0) <= oddp1; -- Odd parity bit

--if (temp6(6) = '0') then

c_28 (27 downto 20) <= dt_tmp(25);
c_28 (19 downto 12) <= dt_tmp(26);
c_28 (11 downto 4) <= dt_tmp(27);
c_28 (3 downto 1) <= temp6(2 downto 0);
c_28 (0) <= oddp2; -- Odd parity bit


end if;
end if;
end process;

data_temp(111 downto 84) <= a_28;
data_temp(83 downto 56) <= b_28;
data_temp(55 downto 28) <= c_28;
data_temp(27 downto 0) <= d_28;

process(rst, clk1, chkxyzh)
begin

if (rst = '1' or ctr = '1') then

data_shift <= data_temp;
elsif rising_edge(clk1) then
if ( ctr = '0') then
data_shift(111 downto 1) <= data_shift(110 downto 0);
data_shift(0) <= '0';

end if;
end if;
end process;
serial_data <= data_shift(111);
end behv;

 

[VHDLguy]

Not sure if you are still working on this, but:

It looks like you do not need an array of 32 entries for dt_tmp. If you keep bit dt_tmp(0)(6) aside you only need an array of maybe 5 entries. Im not sure about the commented out lines, but even if you do need them it would still work with only keeping a small dt_tmp array.

That should cut a big portion of your register usage out. Of course you would need to keep track of addr when you are assignming dt_tmp to a,b,c,d_28, but it shouldn't be too hard, and will probably make that big assigment a lot smaller and easier to read.

I also see that your last process is not quite correct. given that your assignment of data_temp to data_shift is asyncronous, you should include data_temp in the sensitivity list. BTW Intersting way of doing that, but i guess it will work ok.

--

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