Memory implementation - expecting IF

[qwertydump]

Line 39. parse error, unexpected PROCESS, expecting IF

Hi I'm new at VHDL and I'm having trouble trying to write a memory file for a multicycle computer. I'm hoping to write a memory file that would hold instruction and data but I can't even get past the above error.

any help much appreciated
here's my code


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity memory is
--Port( address : in unsigned std_logic_vector(31 downto 0);
Port( address : in unsigned (31 downto 0);
write_data : in std_logic_vector(31 downto 0);
MemWrite, MemRead : in std_logic;
read_data : out std_logic_vactor(31 downto 0));
end memory;


architecture Behavioural of memory is
type mem_array is array(0 to 7) of std_logic_vector(31 downto 0);

begin
mem_process: process(address, write_data)

variable data_mem : mem_Array :=(
X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000");

variable addr:integer;
begin

addr:= conv_integer(address(2 downto 0));

if MemWrite='1'then
data_mem(addr):= write_data;
else if MemRead='1' then
read_data <= data_mem(addr) after 10ns;

end if;
end process;
end Behavioural;


cheers
Simple Jack

 

[Robbe147]

Each "if" should be followed by a "end if"
Now, two constructions are valid:

1)

if MemWrite='1'then
data_mem(addr):= write_data;
else
if MemRead='1' then
read_data <= data_mem(addr) after 10ns;
end if;
end if;


2) (Notice the "elsif" in one word)

if MemWrite='1'then
data_mem(addr):= write_data;
elsif MemRead='1' then
read_data <= data_mem(addr) after 10ns;
end if;