loops in vhdl

[anjaxe1]

I am having problems in for loop etc in vhdl. i use xilinx . does Xilinx support looping? Please let me know.

 

[beemer]

Hi anjaxe1,


Looping is supported in VHDL. Xilinx is a vendor of programmable logic devices, and so they don't really "support" looping, it is VHDL that does that.

As for your issues, what kind of problems are you having??

Beemer

 

[vhdlverilog]

i think u'r question is valid.
which version of xilix r u using?
if u r using trial version,
loops r supported but,
the statements
EXIT,BREAK,NEXT
wont work