Tek-Tips is the largest IT community on the Internet today!

Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!

Register Log in
  • Congratulations Mike Lewis on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!

Loading two-dimensional array via std_logic_vector port

Status
Not open for further replies.
pedjasmek

pedjasmek

Technical User
May 7, 2009
2
RS
Can someone explain to me how can I load two two-dimensional arrays via two std_logic_vector type ports so I could perform simple calculation using them (adding their elements and using the results)?Thanks
 
Status
Not open for further replies.

Similar threads

isamel85
  • Locked
  • Question
Sending binary data from Matlab to FPGA using the serial port
Replies
0
Views
175
isamel85
isamel85
gibsogu
  • Locked
  • Question
Can an out port be set to hi-Z
Replies
0
Views
112
gibsogu
gibsogu
danell
  • Locked
  • Question
Division in VHDL with std_logic_vector
Replies
2
Views
93
PaulieQ
PaulieQ
dorack
  • Locked
  • Question
signal in an array
Replies
2
Views
78
barryvo
barryvo
John5788
  • Locked
  • Question
VHDL bidirectional port questions
Replies
1
Views
76
jeandelfrigo
jeandelfrigo

Part and Inventory Search

Sponsor

Back
Top