poireau2001
Technical User
Hi
I'm a newbie in VHDL. Like many people, i read the book: "VHDL: Learn by examples".
Then, i've been inspired to write for myself a kind FSM able to handle samples from an ADC in a RAM.
If you've got some spear time, i would be glad if you could have a look to the code i wrote (it is not very long). It is written with Xilinx ISE and it has to go on a Spartan 3E (yes, with the Spartan 3E kit in the book).
If you compile synthetise it by yourself, you'll see many warnings. Some, i'm aware of them (like the size of the signals), some i don't undertand, like the latches.
The thing, when i synthetise mini_uC.vhd by itself (as the top design) i have no problem about the latches. Everything is fine.
When i plug something like an entity (in my code the ROM and RAM ctrl) on it, latches are appearing and it cannot find the clk in the timing constraint...
So if you've got some spear time to look at it ... Thank you very much in advance...
I'm a newbie in VHDL. Like many people, i read the book: "VHDL: Learn by examples".
Then, i've been inspired to write for myself a kind FSM able to handle samples from an ADC in a RAM.
If you've got some spear time, i would be glad if you could have a look to the code i wrote (it is not very long). It is written with Xilinx ISE and it has to go on a Spartan 3E (yes, with the Spartan 3E kit in the book).
If you compile synthetise it by yourself, you'll see many warnings. Some, i'm aware of them (like the size of the signals), some i don't undertand, like the latches.
The thing, when i synthetise mini_uC.vhd by itself (as the top design) i have no problem about the latches. Everything is fine.
When i plug something like an entity (in my code the ROM and RAM ctrl) on it, latches are appearing and it cannot find the clk in the timing constraint...
So if you've got some spear time to look at it ... Thank you very much in advance...