LAST_VALUE attribute

[gemstar]

hi there, am trying to synthesis a generic clock divider I have created. it works fine in simulation with modelsim but xilinx syntheses tool xst is not happy. - see code below:


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;


entity generic_clk_divider is
generic
(
g_DIV_VALUE : integer := 5
);

port
(
n_RST : in std_logic;
CLK_IN : in std_logic;
CLK_OUT : out std_logic
);
end entity generic_clk_divider;

architecture RTL of generic_clk_divider is

subtype t_COUNTER is natural range 0 to g_DIV_VALUE*2 - 1;

signal count : t_COUNTER := 0;

begin

clk_gen : process(n_RST, CLK_IN, count)
begin
if((rising_edge(CLK_IN) or falling_edge(CLK_IN)) and count < t_COUNTER'high) then
count <= count + 1;
elsif((rising_edge(CLK_IN) or falling_edge(CLK_IN)) and count = t_COUNTER'high) then
count <= t_COUNTER'low;
end if;

if(count >= (t_COUNTER'HIGH +1)/2) then
CLK_OUT <= '0';
else
CLK_OUT <= '1';
end if;

if(n_RST = '0') then
count <= 0;
end if;
end process clk_gen;

end architecture RTL;

error i get is:

ERROR:Xst:818 - <path_to_File> LAST_VALUE must be used with clk'event condition.

So... i tried changing the lines

if((rising_edge(CLK_IN) or falling_edge(CLK_IN)) and count < t_COUNTER'high) then...

to

if(((CLK_IN'event and CLK_IN = '1') or (CLK_IN'event and CLK_IN = '0')) and count < t_COUNTER'high) then...

but get the same error, so i added the last_value attribute:

if(((CLK_IN'event and CLK_IN = '1' and LAST_VALUE = '0') or (CLK_IN'event and CLK_IN = '0' and LAST_VALUE = '1')) and count < t_COUNTER'high) then..

but now i get an error on the same line saying:
ERROR:HDLParsers:808 - <path_to_File> can not have such operands in this context.

I cannot work out what is going on atall - don't know what the actual initial problem was anyway and am having bigger problems trying to resolve it.

Can anybody enlighten me.. my brain is starting to melt

cheers